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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
| 6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
| 7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
| 8 // | 8 // |
| 9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
| 10 // | 10 // |
| (...skipping 63 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 74 void PrintRd(Instruction* instr); | 74 void PrintRd(Instruction* instr); |
| 75 void PrintFs(Instruction* instr); | 75 void PrintFs(Instruction* instr); |
| 76 void PrintFt(Instruction* instr); | 76 void PrintFt(Instruction* instr); |
| 77 void PrintFd(Instruction* instr); | 77 void PrintFd(Instruction* instr); |
| 78 void PrintSa(Instruction* instr); | 78 void PrintSa(Instruction* instr); |
| 79 void PrintSd(Instruction* instr); | 79 void PrintSd(Instruction* instr); |
| 80 void PrintSs1(Instruction* instr); | 80 void PrintSs1(Instruction* instr); |
| 81 void PrintSs2(Instruction* instr); | 81 void PrintSs2(Instruction* instr); |
| 82 void PrintBc(Instruction* instr); | 82 void PrintBc(Instruction* instr); |
| 83 void PrintCc(Instruction* instr); | 83 void PrintCc(Instruction* instr); |
| 84 void PrintBp2(Instruction* instr); |
| 84 void PrintFunction(Instruction* instr); | 85 void PrintFunction(Instruction* instr); |
| 85 void PrintSecondaryField(Instruction* instr); | 86 void PrintSecondaryField(Instruction* instr); |
| 86 void PrintUImm16(Instruction* instr); | 87 void PrintUImm16(Instruction* instr); |
| 87 void PrintSImm16(Instruction* instr); | 88 void PrintSImm16(Instruction* instr); |
| 88 void PrintXImm16(Instruction* instr); | 89 void PrintXImm16(Instruction* instr); |
| 90 void PrintXImm18(Instruction* instr); |
| 91 void PrintSImm18(Instruction* instr); |
| 92 void PrintXImm19(Instruction* instr); |
| 93 void PrintSImm19(Instruction* instr); |
| 89 void PrintXImm21(Instruction* instr); | 94 void PrintXImm21(Instruction* instr); |
| 95 void PrintSImm21(Instruction* instr); |
| 90 void PrintXImm26(Instruction* instr); | 96 void PrintXImm26(Instruction* instr); |
| 91 void PrintCode(Instruction* instr); // For break and trap instructions. | 97 void PrintCode(Instruction* instr); // For break and trap instructions. |
| 92 void PrintFormat(Instruction* instr); // For floating format postfix. | 98 void PrintFormat(Instruction* instr); // For floating format postfix. |
| 93 // Printing of instruction name. | 99 // Printing of instruction name. |
| 94 void PrintInstructionName(Instruction* instr); | 100 void PrintInstructionName(Instruction* instr); |
| 95 | 101 |
| 96 // Handle formatting of instructions and their options. | 102 // Handle formatting of instructions and their options. |
| 97 int FormatRegister(Instruction* instr, const char* option); | 103 int FormatRegister(Instruction* instr, const char* option); |
| 98 int FormatFPURegister(Instruction* instr, const char* option); | 104 int FormatFPURegister(Instruction* instr, const char* option); |
| 99 int FormatOption(Instruction* instr, const char* option); | 105 int FormatOption(Instruction* instr, const char* option); |
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| 229 } | 235 } |
| 230 | 236 |
| 231 | 237 |
| 232 // Print the integer value of the cc field for the FP compare instructions. | 238 // Print the integer value of the cc field for the FP compare instructions. |
| 233 void Decoder::PrintCc(Instruction* instr) { | 239 void Decoder::PrintCc(Instruction* instr) { |
| 234 int cc = instr->FCccValue(); | 240 int cc = instr->FCccValue(); |
| 235 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "cc(%d)", cc); | 241 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "cc(%d)", cc); |
| 236 } | 242 } |
| 237 | 243 |
| 238 | 244 |
| 245 void Decoder::PrintBp2(Instruction* instr) { |
| 246 int bp2 = instr->Bp2Value(); |
| 247 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", bp2); |
| 248 } |
| 249 |
| 250 |
| 239 // Print 16-bit unsigned immediate value. | 251 // Print 16-bit unsigned immediate value. |
| 240 void Decoder::PrintUImm16(Instruction* instr) { | 252 void Decoder::PrintUImm16(Instruction* instr) { |
| 241 int32_t imm = instr->Imm16Value(); | 253 int32_t imm = instr->Imm16Value(); |
| 242 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm); | 254 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm); |
| 243 } | 255 } |
| 244 | 256 |
| 245 | 257 |
| 246 // Print 16-bit signed immediate value. | 258 // Print 16-bit signed immediate value. |
| 247 void Decoder::PrintSImm16(Instruction* instr) { | 259 void Decoder::PrintSImm16(Instruction* instr) { |
| 248 int32_t imm = ((instr->Imm16Value()) << 16) >> 16; | 260 int32_t imm = ((instr->Imm16Value()) << 16) >> 16; |
| 249 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm); | 261 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm); |
| 250 } | 262 } |
| 251 | 263 |
| 252 | 264 |
| 253 // Print 16-bit hexa immediate value. | 265 // Print 16-bit hexa immediate value. |
| 254 void Decoder::PrintXImm16(Instruction* instr) { | 266 void Decoder::PrintXImm16(Instruction* instr) { |
| 255 int32_t imm = instr->Imm16Value(); | 267 int32_t imm = instr->Imm16Value(); |
| 256 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); | 268 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); |
| 257 } | 269 } |
| 258 | 270 |
| 259 | 271 |
| 272 // Print 18-bit signed immediate value. |
| 273 void Decoder::PrintSImm18(Instruction* instr) { |
| 274 int32_t imm = |
| 275 ((instr->Imm18Value()) << (32 - kImm18Bits)) >> (32 - kImm18Bits); |
| 276 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm); |
| 277 } |
| 278 |
| 279 |
| 280 // Print 18-bit hexa immediate value. |
| 281 void Decoder::PrintXImm18(Instruction* instr) { |
| 282 int32_t imm = instr->Imm18Value(); |
| 283 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); |
| 284 } |
| 285 |
| 286 |
| 287 // Print 19-bit hexa immediate value. |
| 288 void Decoder::PrintXImm19(Instruction* instr) { |
| 289 int32_t imm = instr->Imm19Value(); |
| 290 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); |
| 291 } |
| 292 |
| 293 |
| 294 // Print 19-bit signed immediate value. |
| 295 void Decoder::PrintSImm19(Instruction* instr) { |
| 296 int32_t imm19 = instr->Imm19Value(); |
| 297 // set sign |
| 298 imm19 <<= (32 - kImm19Bits); |
| 299 imm19 >>= (32 - kImm19Bits); |
| 300 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm19); |
| 301 } |
| 302 |
| 303 |
| 260 // Print 21-bit immediate value. | 304 // Print 21-bit immediate value. |
| 261 void Decoder::PrintXImm21(Instruction* instr) { | 305 void Decoder::PrintXImm21(Instruction* instr) { |
| 262 uint32_t imm = instr->Imm21Value(); | 306 uint32_t imm = instr->Imm21Value(); |
| 263 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); | 307 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); |
| 264 } | 308 } |
| 265 | 309 |
| 266 | 310 |
| 311 // Print 21-bit signed immediate value. |
| 312 void Decoder::PrintSImm21(Instruction* instr) { |
| 313 int32_t imm21 = instr->Imm21Value(); |
| 314 // set sign |
| 315 imm21 <<= (32 - kImm21Bits); |
| 316 imm21 >>= (32 - kImm21Bits); |
| 317 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm21); |
| 318 } |
| 319 |
| 320 |
| 267 // Print 26-bit immediate value. | 321 // Print 26-bit immediate value. |
| 268 void Decoder::PrintXImm26(Instruction* instr) { | 322 void Decoder::PrintXImm26(Instruction* instr) { |
| 269 uint32_t imm = instr->Imm26Value() << kImmFieldShift; | 323 uint32_t imm = instr->Imm26Value() << kImmFieldShift; |
| 270 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); | 324 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); |
| 271 } | 325 } |
| 272 | 326 |
| 273 | 327 |
| 274 // Print 26-bit immediate value. | 328 // Print 26-bit immediate value. |
| 275 void Decoder::PrintCode(Instruction* instr) { | 329 void Decoder::PrintCode(Instruction* instr) { |
| 276 if (instr->OpcodeFieldRaw() != SPECIAL) | 330 if (instr->OpcodeFieldRaw() != SPECIAL) |
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| 382 // characters that were consumed from the formatting string. | 436 // characters that were consumed from the formatting string. |
| 383 int Decoder::FormatOption(Instruction* instr, const char* format) { | 437 int Decoder::FormatOption(Instruction* instr, const char* format) { |
| 384 switch (format[0]) { | 438 switch (format[0]) { |
| 385 case 'c': { // 'code for break or trap instructions. | 439 case 'c': { // 'code for break or trap instructions. |
| 386 DCHECK(STRING_STARTS_WITH(format, "code")); | 440 DCHECK(STRING_STARTS_WITH(format, "code")); |
| 387 PrintCode(instr); | 441 PrintCode(instr); |
| 388 return 4; | 442 return 4; |
| 389 } | 443 } |
| 390 case 'i': { // 'imm16u or 'imm26. | 444 case 'i': { // 'imm16u or 'imm26. |
| 391 if (format[3] == '1') { | 445 if (format[3] == '1') { |
| 392 DCHECK(STRING_STARTS_WITH(format, "imm16")); | 446 if (format[4] == '6') { |
| 393 if (format[5] == 's') { | 447 DCHECK(STRING_STARTS_WITH(format, "imm16")); |
| 394 DCHECK(STRING_STARTS_WITH(format, "imm16s")); | 448 switch (format[5]) { |
| 395 PrintSImm16(instr); | 449 case 's': |
| 396 } else if (format[5] == 'u') { | 450 DCHECK(STRING_STARTS_WITH(format, "imm16s")); |
| 397 DCHECK(STRING_STARTS_WITH(format, "imm16u")); | 451 PrintSImm16(instr); |
| 398 PrintSImm16(instr); | 452 break; |
| 399 } else { | 453 case 'u': |
| 400 DCHECK(STRING_STARTS_WITH(format, "imm16x")); | 454 DCHECK(STRING_STARTS_WITH(format, "imm16u")); |
| 401 PrintXImm16(instr); | 455 PrintSImm16(instr); |
| 456 break; |
| 457 case 'x': |
| 458 DCHECK(STRING_STARTS_WITH(format, "imm16x")); |
| 459 PrintXImm16(instr); |
| 460 break; |
| 461 } |
| 462 return 6; |
| 463 } else if (format[4] == '8') { |
| 464 DCHECK(STRING_STARTS_WITH(format, "imm18")); |
| 465 switch (format[5]) { |
| 466 case 's': |
| 467 DCHECK(STRING_STARTS_WITH(format, "imm18s")); |
| 468 PrintSImm18(instr); |
| 469 break; |
| 470 case 'x': |
| 471 DCHECK(STRING_STARTS_WITH(format, "imm18x")); |
| 472 PrintXImm18(instr); |
| 473 break; |
| 474 } |
| 475 return 6; |
| 476 } else if (format[4] == '9') { |
| 477 DCHECK(STRING_STARTS_WITH(format, "imm19")); |
| 478 switch (format[5]) { |
| 479 case 's': |
| 480 DCHECK(STRING_STARTS_WITH(format, "imm19s")); |
| 481 PrintSImm19(instr); |
| 482 break; |
| 483 case 'x': |
| 484 DCHECK(STRING_STARTS_WITH(format, "imm19x")); |
| 485 PrintXImm19(instr); |
| 486 break; |
| 487 } |
| 488 return 6; |
| 402 } | 489 } |
| 403 return 6; | |
| 404 } else if (format[3] == '2' && format[4] == '1') { | 490 } else if (format[3] == '2' && format[4] == '1') { |
| 405 DCHECK(STRING_STARTS_WITH(format, "imm21x")); | 491 DCHECK(STRING_STARTS_WITH(format, "imm21")); |
| 406 PrintXImm21(instr); | 492 switch (format[5]) { |
| 493 case 's': |
| 494 DCHECK(STRING_STARTS_WITH(format, "imm21s")); |
| 495 PrintSImm21(instr); |
| 496 break; |
| 497 case 'x': |
| 498 DCHECK(STRING_STARTS_WITH(format, "imm21x")); |
| 499 PrintXImm21(instr); |
| 500 break; |
| 501 } |
| 407 return 6; | 502 return 6; |
| 408 } else if (format[3] == '2' && format[4] == '6') { | 503 } else if (format[3] == '2' && format[4] == '6') { |
| 409 DCHECK(STRING_STARTS_WITH(format, "imm26x")); | 504 DCHECK(STRING_STARTS_WITH(format, "imm26x")); |
| 410 PrintXImm26(instr); | 505 PrintXImm26(instr); |
| 411 return 6; | 506 return 6; |
| 412 } | 507 } |
| 413 } | 508 } |
| 414 case 'r': { // 'r: registers. | 509 case 'r': { // 'r: registers. |
| 415 return FormatRegister(instr, format); | 510 return FormatRegister(instr, format); |
| 416 } | 511 } |
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| 435 PrintSs1(instr); | 530 PrintSs1(instr); |
| 436 return 3; | 531 return 3; |
| 437 } else { | 532 } else { |
| 438 DCHECK(STRING_STARTS_WITH(format, "ss2")); /* ins size */ | 533 DCHECK(STRING_STARTS_WITH(format, "ss2")); /* ins size */ |
| 439 PrintSs2(instr); | 534 PrintSs2(instr); |
| 440 return 3; | 535 return 3; |
| 441 } | 536 } |
| 442 } | 537 } |
| 443 } | 538 } |
| 444 } | 539 } |
| 445 case 'b': { // 'bc - Special for bc1 cc field. | 540 case 'b': { |
| 446 DCHECK(STRING_STARTS_WITH(format, "bc")); | 541 switch (format[1]) { |
| 447 PrintBc(instr); | 542 case 'c': { // 'bc - Special for bc1 cc field. |
| 448 return 2; | 543 DCHECK(STRING_STARTS_WITH(format, "bc")); |
| 544 PrintBc(instr); |
| 545 return 2; |
| 546 } |
| 547 case 'p': { |
| 548 switch (format[2]) { |
| 549 case '2': { // 'bp2 |
| 550 DCHECK(STRING_STARTS_WITH(format, "bp2")); |
| 551 PrintBp2(instr); |
| 552 return 3; |
| 553 } |
| 554 } |
| 555 } |
| 556 } |
| 449 } | 557 } |
| 450 case 'C': { // 'Cc - Special for c.xx.d cc field. | 558 case 'C': { // 'Cc - Special for c.xx.d cc field. |
| 451 DCHECK(STRING_STARTS_WITH(format, "Cc")); | 559 DCHECK(STRING_STARTS_WITH(format, "Cc")); |
| 452 PrintCc(instr); | 560 PrintCc(instr); |
| 453 return 2; | 561 return 2; |
| 454 } | 562 } |
| 455 case 't': | 563 case 't': |
| 456 PrintFormat(instr); | 564 PrintFormat(instr); |
| 457 return 1; | 565 return 1; |
| 458 } | 566 } |
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| 934 break; | 1042 break; |
| 935 default: | 1043 default: |
| 936 UNREACHABLE(); | 1044 UNREACHABLE(); |
| 937 } | 1045 } |
| 938 } | 1046 } |
| 939 | 1047 |
| 940 | 1048 |
| 941 void Decoder::DecodeTypeRegisterSPECIAL3(Instruction* instr) { | 1049 void Decoder::DecodeTypeRegisterSPECIAL3(Instruction* instr) { |
| 942 switch (instr->FunctionFieldRaw()) { | 1050 switch (instr->FunctionFieldRaw()) { |
| 943 case INS: { | 1051 case INS: { |
| 944 if (IsMipsArchVariant(kMips32r2)) { | 1052 if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) { |
| 945 Format(instr, "ins 'rt, 'rs, 'sa, 'ss2"); | 1053 Format(instr, "ins 'rt, 'rs, 'sa, 'ss2"); |
| 946 } else { | 1054 } else { |
| 947 Unknown(instr); | 1055 Unknown(instr); |
| 948 } | 1056 } |
| 949 break; | 1057 break; |
| 950 } | 1058 } |
| 951 case EXT: { | 1059 case EXT: { |
| 952 if (IsMipsArchVariant(kMips32r2)) { | 1060 if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) { |
| 953 Format(instr, "ext 'rt, 'rs, 'sa, 'ss1"); | 1061 Format(instr, "ext 'rt, 'rs, 'sa, 'ss1"); |
| 954 } else { | 1062 } else { |
| 955 Unknown(instr); | 1063 Unknown(instr); |
| 956 } | 1064 } |
| 957 break; | 1065 break; |
| 958 } | 1066 } |
| 959 case BITSWAP: { | 1067 case BSHFL: { |
| 960 if (IsMipsArchVariant(kMips32r6)) { | 1068 int sa = instr->SaFieldRaw() >> kSaShift; |
| 961 Format(instr, "bitswap 'rd, 'rt"); | 1069 switch (sa) { |
| 962 } else { | 1070 case BITSWAP: { |
| 963 Unknown(instr); | 1071 if (IsMipsArchVariant(kMips32r6)) { |
| 1072 Format(instr, "bitswap 'rd, 'rt"); |
| 1073 } else { |
| 1074 Unknown(instr); |
| 1075 } |
| 1076 break; |
| 1077 } |
| 1078 case SEB: |
| 1079 case SEH: |
| 1080 case WSBH: |
| 1081 UNREACHABLE(); |
| 1082 break; |
| 1083 default: { |
| 1084 sa >>= kBp2Bits; |
| 1085 switch (sa) { |
| 1086 case ALIGN: { |
| 1087 if (IsMipsArchVariant(kMips32r6)) { |
| 1088 Format(instr, "align 'rd, 'rs, 'rt, 'bp2"); |
| 1089 } else { |
| 1090 Unknown(instr); |
| 1091 } |
| 1092 break; |
| 1093 } |
| 1094 default: |
| 1095 UNREACHABLE(); |
| 1096 break; |
| 1097 } |
| 1098 } |
| 964 } | 1099 } |
| 965 break; | 1100 break; |
| 966 } | 1101 } |
| 967 default: | 1102 default: |
| 968 UNREACHABLE(); | 1103 UNREACHABLE(); |
| 969 } | 1104 } |
| 970 } | 1105 } |
| 971 | 1106 |
| 972 | 1107 |
| 973 void Decoder::DecodeTypeRegister(Instruction* instr) { | 1108 void Decoder::DecodeTypeRegister(Instruction* instr) { |
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| 1145 } else if ((instr->RtFieldRaw() != instr->RsFieldRaw()) | 1280 } else if ((instr->RtFieldRaw() != instr->RsFieldRaw()) |
| 1146 && (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) { | 1281 && (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) { |
| 1147 Format(instr, "bltc 'rs, 'rt, 'imm16u"); | 1282 Format(instr, "bltc 'rs, 'rt, 'imm16u"); |
| 1148 } else if ((instr->RsFieldRaw() == 0) | 1283 } else if ((instr->RsFieldRaw() == 0) |
| 1149 && (instr->RtFieldRaw() != 0)) { | 1284 && (instr->RtFieldRaw() != 0)) { |
| 1150 Format(instr, "bgtzc 'rt, 'imm16u"); | 1285 Format(instr, "bgtzc 'rt, 'imm16u"); |
| 1151 } else { | 1286 } else { |
| 1152 UNREACHABLE(); | 1287 UNREACHABLE(); |
| 1153 } | 1288 } |
| 1154 break; | 1289 break; |
| 1155 case BEQZC: | 1290 case POP66: |
| 1156 if (instr->RsFieldRaw() != 0) { | 1291 if (instr->RsValue() == JIC) { |
| 1157 Format(instr, "beqzc 'rs, 'imm21x"); | 1292 Format(instr, "jic 'rt, 'imm16s"); |
| 1293 } else { |
| 1294 Format(instr, "beqzc 'rs, 'imm21s"); |
| 1158 } | 1295 } |
| 1159 break; | 1296 break; |
| 1160 case BNEZC: | 1297 case POP76: |
| 1161 if (instr->RsFieldRaw() != 0) { | 1298 if (instr->RsValue() == JIALC) { |
| 1299 Format(instr, "jialc 'rt, 'imm16x"); |
| 1300 } else { |
| 1162 Format(instr, "bnezc 'rs, 'imm21x"); | 1301 Format(instr, "bnezc 'rs, 'imm21x"); |
| 1163 } | 1302 } |
| 1164 break; | 1303 break; |
| 1165 // ------------- Arithmetic instructions. | 1304 // ------------- Arithmetic instructions. |
| 1166 case ADDI: | 1305 case ADDI: |
| 1167 if (!IsMipsArchVariant(kMips32r6)) { | 1306 if (!IsMipsArchVariant(kMips32r6)) { |
| 1168 Format(instr, "addi 'rt, 'rs, 'imm16s"); | 1307 Format(instr, "addi 'rt, 'rs, 'imm16s"); |
| 1169 } else { | 1308 } else { |
| 1170 // Check if BOVC or BEQC instruction. | 1309 // Check if BOVC or BEQC instruction. |
| 1171 if (instr->RsFieldRaw() >= instr->RtFieldRaw()) { | 1310 if (instr->RsFieldRaw() >= instr->RtFieldRaw()) { |
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| 1263 break; | 1402 break; |
| 1264 case LDC1: | 1403 case LDC1: |
| 1265 Format(instr, "ldc1 'ft, 'imm16s('rs)"); | 1404 Format(instr, "ldc1 'ft, 'imm16s('rs)"); |
| 1266 break; | 1405 break; |
| 1267 case SWC1: | 1406 case SWC1: |
| 1268 Format(instr, "swc1 'ft, 'imm16s('rs)"); | 1407 Format(instr, "swc1 'ft, 'imm16s('rs)"); |
| 1269 break; | 1408 break; |
| 1270 case SDC1: | 1409 case SDC1: |
| 1271 Format(instr, "sdc1 'ft, 'imm16s('rs)"); | 1410 Format(instr, "sdc1 'ft, 'imm16s('rs)"); |
| 1272 break; | 1411 break; |
| 1412 case PCREL: { |
| 1413 int32_t imm21 = instr->Imm21Value(); |
| 1414 // rt field: 5-bits checking |
| 1415 uint8_t rt = (imm21 >> kImm16Bits); |
| 1416 switch (rt) { |
| 1417 case ALUIPC: |
| 1418 Format(instr, "aluipc 'rs, 'imm16s"); |
| 1419 break; |
| 1420 case AUIPC: |
| 1421 UNREACHABLE(); |
| 1422 break; |
| 1423 default: { |
| 1424 // rt field: checking of the most significant 2-bits |
| 1425 rt = (imm21 >> kImm19Bits); |
| 1426 switch (rt) { |
| 1427 case LWPC: |
| 1428 Format(instr, "lwpc 'rs, 'imm19s"); |
| 1429 break; |
| 1430 case ADDIUPC: |
| 1431 Format(instr, "addiupc 'rs, 'imm19s"); |
| 1432 break; |
| 1433 default: |
| 1434 UNREACHABLE(); |
| 1435 break; |
| 1436 } |
| 1437 } |
| 1438 } |
| 1439 break; |
| 1440 } |
| 1273 default: | 1441 default: |
| 1274 printf("a 0x%x \n", instr->OpcodeFieldRaw()); | 1442 printf("a 0x%x \n", instr->OpcodeFieldRaw()); |
| 1275 UNREACHABLE(); | 1443 UNREACHABLE(); |
| 1276 break; | 1444 break; |
| 1277 } | 1445 } |
| 1278 } | 1446 } |
| 1279 | 1447 |
| 1280 | 1448 |
| 1281 void Decoder::DecodeTypeJump(Instruction* instr) { | 1449 void Decoder::DecodeTypeJump(Instruction* instr) { |
| 1282 switch (instr->OpcodeFieldRaw()) { | 1450 switch (instr->OpcodeFieldRaw()) { |
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| 1397 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1565 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
| 1398 } | 1566 } |
| 1399 } | 1567 } |
| 1400 | 1568 |
| 1401 | 1569 |
| 1402 #undef UNSUPPORTED | 1570 #undef UNSUPPORTED |
| 1403 | 1571 |
| 1404 } // namespace disasm | 1572 } // namespace disasm |
| 1405 | 1573 |
| 1406 #endif // V8_TARGET_ARCH_MIPS | 1574 #endif // V8_TARGET_ARCH_MIPS |
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