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| 1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #include "src/v8.h" | 5 #include "src/v8.h" |
| 6 | 6 |
| 7 #if V8_TARGET_ARCH_ARM64 | 7 #if V8_TARGET_ARCH_ARM64 |
| 8 | 8 |
| 9 #include "src/codegen.h" | 9 #include "src/codegen.h" |
| 10 #include "src/ic/ic.h" | 10 #include "src/ic/ic.h" |
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| 361 __ Bind(&slow); | 361 __ Bind(&slow); |
| 362 GenerateRuntimeGetProperty(masm); | 362 GenerateRuntimeGetProperty(masm); |
| 363 } | 363 } |
| 364 | 364 |
| 365 | 365 |
| 366 void LoadIC::GenerateMiss(MacroAssembler* masm) { | 366 void LoadIC::GenerateMiss(MacroAssembler* masm) { |
| 367 // The return address is in lr. | 367 // The return address is in lr. |
| 368 Isolate* isolate = masm->isolate(); | 368 Isolate* isolate = masm->isolate(); |
| 369 ASM_LOCATION("LoadIC::GenerateMiss"); | 369 ASM_LOCATION("LoadIC::GenerateMiss"); |
| 370 | 370 |
| 371 DCHECK(!AreAliased(x4, x5, VectorLoadICDescriptor::SlotRegister(), | 371 DCHECK(!AreAliased(x4, x5, LoadWithVectorDescriptor::SlotRegister(), |
| 372 VectorLoadICDescriptor::VectorRegister())); | 372 LoadWithVectorDescriptor::VectorRegister())); |
| 373 __ IncrementCounter(isolate->counters()->load_miss(), 1, x4, x5); | 373 __ IncrementCounter(isolate->counters()->load_miss(), 1, x4, x5); |
| 374 | 374 |
| 375 // Perform tail call to the entry. | 375 // Perform tail call to the entry. |
| 376 __ Push(VectorLoadICDescriptor::ReceiverRegister(), | 376 __ Push(LoadWithVectorDescriptor::ReceiverRegister(), |
| 377 VectorLoadICDescriptor::NameRegister(), | 377 LoadWithVectorDescriptor::NameRegister(), |
| 378 VectorLoadICDescriptor::SlotRegister(), | 378 LoadWithVectorDescriptor::SlotRegister(), |
| 379 VectorLoadICDescriptor::VectorRegister()); | 379 LoadWithVectorDescriptor::VectorRegister()); |
| 380 ExternalReference ref = ExternalReference(IC_Utility(kLoadIC_Miss), isolate); | 380 ExternalReference ref = ExternalReference(IC_Utility(kLoadIC_Miss), isolate); |
| 381 int arg_count = 4; | 381 int arg_count = 4; |
| 382 __ TailCallExternalReference(ref, arg_count, 1); | 382 __ TailCallExternalReference(ref, arg_count, 1); |
| 383 } | 383 } |
| 384 | 384 |
| 385 | 385 |
| 386 void LoadIC::GenerateRuntimeGetProperty(MacroAssembler* masm) { | 386 void LoadIC::GenerateRuntimeGetProperty(MacroAssembler* masm) { |
| 387 // The return address is in lr. | 387 // The return address is in lr. |
| 388 __ Push(LoadDescriptor::ReceiverRegister(), LoadDescriptor::NameRegister()); | 388 __ Push(LoadDescriptor::ReceiverRegister(), LoadDescriptor::NameRegister()); |
| 389 __ TailCallRuntime(Runtime::kGetProperty, 2, 1); | 389 __ TailCallRuntime(Runtime::kGetProperty, 2, 1); |
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| 433 __ Ret(); | 433 __ Ret(); |
| 434 __ Bind(&slow); | 434 __ Bind(&slow); |
| 435 GenerateMiss(masm); | 435 GenerateMiss(masm); |
| 436 } | 436 } |
| 437 | 437 |
| 438 | 438 |
| 439 void KeyedLoadIC::GenerateMiss(MacroAssembler* masm) { | 439 void KeyedLoadIC::GenerateMiss(MacroAssembler* masm) { |
| 440 // The return address is in lr. | 440 // The return address is in lr. |
| 441 Isolate* isolate = masm->isolate(); | 441 Isolate* isolate = masm->isolate(); |
| 442 | 442 |
| 443 DCHECK(!AreAliased(x10, x11, VectorLoadICDescriptor::SlotRegister(), | 443 DCHECK(!AreAliased(x10, x11, LoadWithVectorDescriptor::SlotRegister(), |
| 444 VectorLoadICDescriptor::VectorRegister())); | 444 LoadWithVectorDescriptor::VectorRegister())); |
| 445 __ IncrementCounter(isolate->counters()->keyed_load_miss(), 1, x10, x11); | 445 __ IncrementCounter(isolate->counters()->keyed_load_miss(), 1, x10, x11); |
| 446 | 446 |
| 447 __ Push(VectorLoadICDescriptor::ReceiverRegister(), | 447 __ Push(LoadWithVectorDescriptor::ReceiverRegister(), |
| 448 VectorLoadICDescriptor::NameRegister(), | 448 LoadWithVectorDescriptor::NameRegister(), |
| 449 VectorLoadICDescriptor::SlotRegister(), | 449 LoadWithVectorDescriptor::SlotRegister(), |
| 450 VectorLoadICDescriptor::VectorRegister()); | 450 LoadWithVectorDescriptor::VectorRegister()); |
| 451 | 451 |
| 452 // Perform tail call to the entry. | 452 // Perform tail call to the entry. |
| 453 ExternalReference ref = | 453 ExternalReference ref = |
| 454 ExternalReference(IC_Utility(kKeyedLoadIC_Miss), isolate); | 454 ExternalReference(IC_Utility(kKeyedLoadIC_Miss), isolate); |
| 455 int arg_count = 4; | 455 int arg_count = 4; |
| 456 __ TailCallExternalReference(ref, arg_count, 1); | 456 __ TailCallExternalReference(ref, arg_count, 1); |
| 457 } | 457 } |
| 458 | 458 |
| 459 | 459 |
| 460 void KeyedLoadIC::GenerateRuntimeGetProperty(MacroAssembler* masm) { | 460 void KeyedLoadIC::GenerateRuntimeGetProperty(MacroAssembler* masm) { |
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| 518 Map::kHasNamedInterceptor, slow); | 518 Map::kHasNamedInterceptor, slow); |
| 519 | 519 |
| 520 // If the receiver is a fast-case object, check the stub cache. Otherwise | 520 // If the receiver is a fast-case object, check the stub cache. Otherwise |
| 521 // probe the dictionary. | 521 // probe the dictionary. |
| 522 __ Ldr(scratch2, FieldMemOperand(receiver, JSObject::kPropertiesOffset)); | 522 __ Ldr(scratch2, FieldMemOperand(receiver, JSObject::kPropertiesOffset)); |
| 523 __ Ldr(scratch3, FieldMemOperand(scratch2, HeapObject::kMapOffset)); | 523 __ Ldr(scratch3, FieldMemOperand(scratch2, HeapObject::kMapOffset)); |
| 524 __ JumpIfRoot(scratch3, Heap::kHashTableMapRootIndex, &probe_dictionary); | 524 __ JumpIfRoot(scratch3, Heap::kHashTableMapRootIndex, &probe_dictionary); |
| 525 | 525 |
| 526 // The handlers in the stub cache expect a vector and slot. Since we won't | 526 // The handlers in the stub cache expect a vector and slot. Since we won't |
| 527 // change the IC from any downstream misses, a dummy vector can be used. | 527 // change the IC from any downstream misses, a dummy vector can be used. |
| 528 Register vector = VectorLoadICDescriptor::VectorRegister(); | 528 Register vector = LoadWithVectorDescriptor::VectorRegister(); |
| 529 Register slot = VectorLoadICDescriptor::SlotRegister(); | 529 Register slot = LoadWithVectorDescriptor::SlotRegister(); |
| 530 DCHECK(!AreAliased(vector, slot, scratch1, scratch2, scratch3, scratch4)); | 530 DCHECK(!AreAliased(vector, slot, scratch1, scratch2, scratch3, scratch4)); |
| 531 Handle<TypeFeedbackVector> dummy_vector = Handle<TypeFeedbackVector>::cast( | 531 Handle<TypeFeedbackVector> dummy_vector = Handle<TypeFeedbackVector>::cast( |
| 532 masm->isolate()->factory()->keyed_load_dummy_vector()); | 532 masm->isolate()->factory()->keyed_load_dummy_vector()); |
| 533 int int_slot = dummy_vector->GetIndex(FeedbackVectorICSlot(0)); | 533 int int_slot = dummy_vector->GetIndex(FeedbackVectorICSlot(0)); |
| 534 __ LoadRoot(vector, Heap::kKeyedLoadDummyVectorRootIndex); | 534 __ LoadRoot(vector, Heap::kKeyedLoadDummyVectorRootIndex); |
| 535 __ Mov(slot, Operand(Smi::FromInt(int_slot))); | 535 __ Mov(slot, Operand(Smi::FromInt(int_slot))); |
| 536 | 536 |
| 537 Code::Flags flags = Code::RemoveTypeAndHolderFromFlags( | 537 Code::Flags flags = Code::RemoveTypeAndHolderFromFlags( |
| 538 Code::ComputeHandlerFlags(Code::LOAD_IC)); | 538 Code::ComputeHandlerFlags(Code::LOAD_IC)); |
| 539 masm->isolate()->stub_cache()->GenerateProbe(masm, Code::KEYED_LOAD_IC, flags, | 539 masm->isolate()->stub_cache()->GenerateProbe(masm, Code::KEYED_LOAD_IC, flags, |
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| 981 } else { | 981 } else { |
| 982 DCHECK(to_patch->Mask(TestBranchMask) == TBNZ); | 982 DCHECK(to_patch->Mask(TestBranchMask) == TBNZ); |
| 983 // This is JumpIfSmi(smi_reg, branch_imm). | 983 // This is JumpIfSmi(smi_reg, branch_imm). |
| 984 patcher.tbz(smi_reg, 0, branch_imm); | 984 patcher.tbz(smi_reg, 0, branch_imm); |
| 985 } | 985 } |
| 986 } | 986 } |
| 987 } | 987 } |
| 988 } // namespace v8::internal | 988 } // namespace v8::internal |
| 989 | 989 |
| 990 #endif // V8_TARGET_ARCH_ARM64 | 990 #endif // V8_TARGET_ARCH_ARM64 |
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