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Issue 1143473003: Revert of MIPS: Add float instructions and test coverage, part one (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 7 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // A Disassembler object is used to disassemble a block of code instruction by 5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be 6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses. 7 // overriden to modify register names or to do symbol lookup on addresses.
8 // 8 //
9 // The example below will disassemble a block of code and print it to stdout. 9 // The example below will disassemble a block of code and print it to stdout.
10 // 10 //
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513 return Instruction::kInstrSize; 513 return Instruction::kInstrSize;
514 } 514 }
515 } 515 }
516 516
517 517
518 bool Decoder::DecodeTypeRegisterRsType(Instruction* instr) { 518 bool Decoder::DecodeTypeRegisterRsType(Instruction* instr) {
519 switch (instr->FunctionFieldRaw()) { 519 switch (instr->FunctionFieldRaw()) {
520 case RINT: 520 case RINT:
521 Format(instr, "rint.'t 'fd, 'fs"); 521 Format(instr, "rint.'t 'fd, 'fs");
522 break; 522 break;
523 case SEL:
524 Format(instr, "sel.'t 'fd, 'fs, 'ft");
525 break;
526 case SELEQZ_C: 523 case SELEQZ_C:
527 Format(instr, "seleqz.'t 'fd, 'fs, 'ft"); 524 Format(instr, "seleqz.'t 'fd, 'fs, 'ft");
528 break; 525 break;
529 case SELNEZ_C: 526 case SELNEZ_C:
530 Format(instr, "selnez.'t 'fd, 'fs, 'ft"); 527 Format(instr, "selnez.'t 'fd, 'fs, 'ft");
531 break; 528 break;
532 case MOVZ_C:
533 Format(instr, "movz.'t 'fd, 'fs, 'rt");
534 break;
535 case MOVN_C:
536 Format(instr, "movn.'t 'fd, 'fs, 'rt");
537 break;
538 case MOVF:
539 if (instr->Bit(16)) {
540 Format(instr, "movt.'t 'fd, 'fs, 'Cc");
541 } else {
542 Format(instr, "movf.'t 'fd, 'fs, 'Cc");
543 }
544 break;
545 case MIN: 529 case MIN:
546 Format(instr, "min.'t 'fd, 'fs, 'ft"); 530 Format(instr, "min.'t 'fd, 'fs, 'ft");
547 break; 531 break;
548 case MAX: 532 case MAX:
549 Format(instr, "max.'t 'fd, 'fs, 'ft"); 533 Format(instr, "max.'t 'fd, 'fs, 'ft");
550 break; 534 break;
551 case MINA: 535 case MINA:
552 Format(instr, "mina.'t 'fd, 'fs, 'ft"); 536 Format(instr, "mina.'t 'fd, 'fs, 'ft");
553 break; 537 break;
554 case MAXA: 538 case MAXA:
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571 break; 555 break;
572 case MOV_D: 556 case MOV_D:
573 Format(instr, "mov.'t 'fd, 'fs"); 557 Format(instr, "mov.'t 'fd, 'fs");
574 break; 558 break;
575 case NEG_D: 559 case NEG_D:
576 Format(instr, "neg.'t 'fd, 'fs"); 560 Format(instr, "neg.'t 'fd, 'fs");
577 break; 561 break;
578 case SQRT_D: 562 case SQRT_D:
579 Format(instr, "sqrt.'t 'fd, 'fs"); 563 Format(instr, "sqrt.'t 'fd, 'fs");
580 break; 564 break;
581 case RECIP_D:
582 Format(instr, "recip.'t 'fd, 'fs");
583 break;
584 case RSQRT_D:
585 Format(instr, "rsqrt.'t 'fd, 'fs");
586 break;
587 case CVT_W_D: 565 case CVT_W_D:
588 Format(instr, "cvt.w.'t 'fd, 'fs"); 566 Format(instr, "cvt.w.'t 'fd, 'fs");
589 break; 567 break;
590 case CVT_L_D: 568 case CVT_L_D:
591 Format(instr, "cvt.l.'t 'fd, 'fs"); 569 Format(instr, "cvt.l.'t 'fd, 'fs");
592 break; 570 break;
593 case TRUNC_W_D: 571 case TRUNC_W_D:
594 Format(instr, "trunc.w.'t 'fd, 'fs"); 572 Format(instr, "trunc.w.'t 'fd, 'fs");
595 break; 573 break;
596 case TRUNC_L_D: 574 case TRUNC_L_D:
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1563 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 1541 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1564 } 1542 }
1565 } 1543 }
1566 1544
1567 1545
1568 #undef UNSUPPORTED 1546 #undef UNSUPPORTED
1569 1547
1570 } // namespace disasm 1548 } // namespace disasm
1571 1549
1572 #endif // V8_TARGET_ARCH_MIPS64 1550 #endif // V8_TARGET_ARCH_MIPS64
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