OLD | NEW |
1 ; This is a test of C-level conversion operations that clang lowers | 1 ; This is a test of C-level conversion operations that clang lowers |
2 ; into pairs of shifts. | 2 ; into pairs of shifts. |
3 | 3 |
4 ; RUN: %p2i -i %s --filetype=obj --disassemble --no-local-syms --args -O2 \ | 4 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ |
5 ; RUN: | FileCheck %s | 5 ; RUN: --target x8632 -i %s --args -O2 \ |
6 ; RUN: %p2i -i %s --filetype=obj --disassemble --no-local-syms --args -Om1 \ | 6 ; RUN: | %if --need=target_X8632 --command FileCheck %s |
7 ; RUN: | FileCheck %s | 7 |
| 8 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ |
| 9 ; RUN: --target x8632 -i %s --args -Om1 \ |
| 10 ; RUN: | %if --need=target_X8632 --command FileCheck %s |
| 11 |
| 12 ; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented) |
| 13 ; once enough infrastructure is in. Also, switch to --filetype=obj |
| 14 ; when possible. |
| 15 ; RUN: %if --need=target_ARM32 --command %p2i --filetype=asm --assemble \ |
| 16 ; RUN: --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \ |
| 17 ; RUN: | %if --need=target_ARM32 --command FileCheck --check-prefix ARM32 %s |
| 18 |
| 19 ; RUN: %if --need=target_ARM32 --command %p2i --filetype=asm --assemble \ |
| 20 ; RUN: --disassemble --target arm32 -i %s --args -Om1 --skip-unimplemented \ |
| 21 ; RUN: | %if --need=target_ARM32 --command FileCheck --check-prefix ARM32 %s |
| 22 |
8 | 23 |
9 @i1 = internal global [4 x i8] zeroinitializer, align 4 | 24 @i1 = internal global [4 x i8] zeroinitializer, align 4 |
10 @i2 = internal global [4 x i8] zeroinitializer, align 4 | 25 @i2 = internal global [4 x i8] zeroinitializer, align 4 |
11 @u1 = internal global [4 x i8] zeroinitializer, align 4 | 26 @u1 = internal global [4 x i8] zeroinitializer, align 4 |
12 | 27 |
13 define void @conv1() { | 28 define void @conv1() { |
14 entry: | 29 entry: |
15 %__0 = bitcast [4 x i8]* @u1 to i32* | 30 %__0 = bitcast [4 x i8]* @u1 to i32* |
16 %v0 = load i32, i32* %__0, align 1 | 31 %v0 = load i32, i32* %__0, align 1 |
17 %sext = shl i32 %v0, 24 | 32 %sext = shl i32 %v0, 24 |
18 %v1 = ashr i32 %sext, 24 | 33 %v1 = ashr i32 %sext, 24 |
19 %__4 = bitcast [4 x i8]* @i1 to i32* | 34 %__4 = bitcast [4 x i8]* @i1 to i32* |
20 store i32 %v1, i32* %__4, align 1 | 35 store i32 %v1, i32* %__4, align 1 |
21 ret void | 36 ret void |
22 } | 37 } |
23 ; CHECK-LABEL: conv1 | 38 ; CHECK-LABEL: conv1 |
24 ; CHECK: shl {{.*}},0x18 | 39 ; CHECK: shl {{.*}},0x18 |
25 ; CHECK: sar {{.*}},0x18 | 40 ; CHECK: sar {{.*}},0x18 |
26 | 41 |
| 42 ; ARM32-LABEL: conv1 |
| 43 ; ARM32: lsl {{.*}}, #24 |
| 44 ; ARM32: asr {{.*}}, #24 |
| 45 |
27 define void @conv2() { | 46 define void @conv2() { |
28 entry: | 47 entry: |
29 %__0 = bitcast [4 x i8]* @u1 to i32* | 48 %__0 = bitcast [4 x i8]* @u1 to i32* |
30 %v0 = load i32, i32* %__0, align 1 | 49 %v0 = load i32, i32* %__0, align 1 |
31 %sext1 = shl i32 %v0, 16 | 50 %sext1 = shl i32 %v0, 16 |
32 %v1 = ashr i32 %sext1, 16 | 51 %v1 = lshr i32 %sext1, 16 |
33 %__4 = bitcast [4 x i8]* @i2 to i32* | 52 %__4 = bitcast [4 x i8]* @i2 to i32* |
34 store i32 %v1, i32* %__4, align 1 | 53 store i32 %v1, i32* %__4, align 1 |
35 ret void | 54 ret void |
36 } | 55 } |
37 ; CHECK-LABEL: conv2 | 56 ; CHECK-LABEL: conv2 |
38 ; CHECK: shl {{.*}},0x10 | 57 ; CHECK: shl {{.*}},0x10 |
39 ; CHECK: sar {{.*}},0x10 | 58 ; CHECK: shr {{.*}},0x10 |
| 59 |
| 60 ; ARM32-LABEL: conv2 |
| 61 ; ARM32: lsl {{.*}}, #16 |
| 62 ; ARM32: lsr {{.*}}, #16 |
OLD | NEW |