Subzero ARM32: Lower shift and zext, sext, and trunc.

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 \
@@ skipping 322 matching lines @@
 ; CHECK: shl e
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ;
 ; OPTM1-LABEL: shl64BitSigned
 ; OPTM1: shld
 ; OPTM1: shl e
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 
+; ARM32-LABEL: shl64BitSigned
+; ARM32: sub [[REG3:r.*]], [[REG2:r.*]], #32
+; ARM32: lsl [[REG1:r.*]], {{r.*}}, [[REG2]]
+; ARM32: orr [[REG1]], [[REG1]], [[REG0:r.*]], lsl [[REG3]]
+; ARM32: rsb [[REG4:r.*]], [[REG2]], #32
+; ARM32: orr [[REG1]], [[REG1]], [[REG0]], lsr [[REG4]]
+; ARM32: lsl {{.*}}, [[REG0]], [[REG2]]
+
 define internal i32 @shl64BitSignedTrunc(i64 %a, i64 %b) {
 entry:
   %shl = shl i64 %a, %b
   %result = trunc i64 %shl to i32
   ret i32 %result
 }
 ; CHECK-LABEL: shl64BitSignedTrunc
 ; CHECK: mov
 ; CHECK: shl e
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ;
 ; OPTM1-LABEL: shl64BitSignedTrunc
 ; OPTM1: shld
 ; OPTM1: shl e
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 
+; ARM32-LABEL: shl64BitSignedTrunc
+; ARM32: lsl r
+
 define internal i64 @shl64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %shl = shl i64 %a, %b
   ret i64 %shl
 }
 ; CHECK-LABEL: shl64BitUnsigned
 ; CHECK: shld
 ; CHECK: shl e
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ;
 ; OPTM1-LABEL: shl64BitUnsigned
 ; OPTM1: shld
 ; OPTM1: shl e
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 
+; ARM32-LABEL: shl64BitUnsigned
+; ARM32: sub
+; ARM32: lsl
+; ARM32: orr
+; ARM32: rsb
+; ARM32: orr
+; ARM32: lsl
+
 define internal i64 @shr64BitSigned(i64 %a, i64 %b) {
 entry:
   %shr = ashr i64 %a, %b
   ret i64 %shr
 }
 ; CHECK-LABEL: shr64BitSigned
 ; CHECK: shrd
 ; CHECK: sar
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: shr64BitSigned
 ; OPTM1: shrd
 ; OPTM1: sar
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 ; OPTM1: sar {{.*}},0x1f
 
+; ARM32-LABEL: shr64BitSigned
+; ARM32: rsb
+; ARM32: lsr
+; ARM32: orr
+; ARM32: subs
+; ARM32: orrpl
+; ARM32: asr
+
 define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) {
 entry:
   %shr = ashr i64 %a, %b
   %result = trunc i64 %shr to i32
   ret i32 %result
 }
 ; CHECK-LABEL: shr64BitSignedTrunc
 ; CHECK: shrd
 ; CHECK: sar
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ;
 ; OPTM1-LABEL: shr64BitSignedTrunc
 ; OPTM1: shrd
 ; OPTM1: sar
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 ; OPTM1: sar {{.*}},0x1f
 
+; ARM32-LABEL: shr64BitSignedTrunc
+; ARM32: rsb
+; ARM32: lsr
+; ARM32: orr
+; ARM32: subs
+; ARM32: orrpl
+
 define internal i64 @shr64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %shr = lshr i64 %a, %b
   ret i64 %shr
 }
 ; CHECK-LABEL: shr64BitUnsigned
 ; CHECK: shrd
 ; CHECK: shr
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ;
 ; OPTM1-LABEL: shr64BitUnsigned
 ; OPTM1: shrd
 ; OPTM1: shr
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 
+; ARM32-LABEL: shr64BitUnsigned
+; ARM32: rsb
+; ARM32: lsr
+; ARM32: orr
+; ARM32: sub
+; ARM32: orr
+; ARM32: lsr
+
 define internal i32 @shr64BitUnsignedTrunc(i64 %a, i64 %b) {
 entry:
   %shr = lshr i64 %a, %b
   %result = trunc i64 %shr to i32
   ret i32 %result
 }
 ; CHECK-LABEL: shr64BitUnsignedTrunc
 ; CHECK: shrd
 ; CHECK: shr
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ;
 ; OPTM1-LABEL: shr64BitUnsignedTrunc
 ; OPTM1: shrd
 ; OPTM1: shr
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 
+; ARM32-LABEL: shr64BitUnsignedTrunc
+; ARM32: rsb
+; ARM32: lsr
+; ARM32: orr
+; ARM32: sub
+; ARM32: orr
+
 define internal i64 @and64BitSigned(i64 %a, i64 %b) {
 entry:
   %and = and i64 %b, %a
   ret i64 %and
 }
 ; CHECK-LABEL: and64BitSigned
 ; CHECK: and
 ; CHECK: and
 ;
 ; OPTM1-LABEL: and64BitSigned
@@ skipping 82 matching lines @@
 ; CHECK: xor
 ;
 ; OPTM1-LABEL: xor64BitUnsigned
 ; OPTM1: xor
 ; OPTM1: xor
 
 ; ARM32-LABEL: xor64BitUnsigned
 ; ARM32: eor
 ; ARM32: eor
 
-define internal i32 @trunc64To32Signed(i64 %a) {
+define internal i32 @trunc64To32Signed(i64 %padding, i64 %a) {
 entry:
   %conv = trunc i64 %a to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: trunc64To32Signed
-; CHECK: mov     eax,DWORD PTR [esp+0x4]
+; CHECK: mov     eax,DWORD PTR [esp+0xc]
 ;
 ; OPTM1-LABEL: trunc64To32Signed
 ; OPTM1: mov     eax,DWORD PTR [esp+
 
+; ARM32-LABEL: trunc64To32Signed
+; ARM32: mov r0, r2
+
 define internal i32 @trunc64To16Signed(i64 %a) {
 entry:
   %conv = trunc i64 %a to i16
   %conv.ret_ext = sext i16 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To16Signed
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK-NEXT: movsx  eax,ax
 ;
 ; OPTM1-LABEL: trunc64To16Signed
 ; OPTM1:      mov     eax,DWORD PTR [esp+
 ; OPTM1: movsx  eax,
 
+; ARM32-LABEL: trunc64To16Signed
+; ARM32: sxth r0, r0
+
 define internal i32 @trunc64To8Signed(i64 %a) {
 entry:
   %conv = trunc i64 %a to i8
   %conv.ret_ext = sext i8 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To8Signed
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK-NEXT: movsx  eax,al
 ;
 ; OPTM1-LABEL: trunc64To8Signed
 ; OPTM1:      mov     eax,DWORD PTR [esp+
 ; OPTM1: movsx  eax,
 
+; ARM32-LABEL: trunc64To8Signed
+; ARM32: sxtb r0, r0
+
 define internal i32 @trunc64To32SignedConst() {
 entry:
   %conv = trunc i64 12345678901234 to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: trunc64To32SignedConst
 ; CHECK: mov eax,0x73ce2ff2
 ;
 ; OPTM1-LABEL: trunc64To32SignedConst
 ; OPTM1: mov eax,0x73ce2ff2
 
+; ARM32-LABEL: trunc64To32SignedConst
+; ARM32: movw r0, #12274 ; 0x2ff2
+; ARM32: movt r0, #29646 ; 0x73ce
+
 define internal i32 @trunc64To16SignedConst() {
 entry:
   %conv = trunc i64 12345678901234 to i16
   %conv.ret_ext = sext i16 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To16SignedConst
 ; CHECK: mov eax,0x73ce2ff2
 ; CHECK: movsx eax,ax
 ;
 ; OPTM1-LABEL: trunc64To16SignedConst
 ; OPTM1: mov eax,0x73ce2ff2
 ; OPTM1: movsx eax,
 
-define internal i32 @trunc64To32Unsigned(i64 %a) {
+; ARM32-LABEL: trunc64To16SignedConst
+; ARM32: movw r0, #12274 ; 0x2ff2
+; ARM32: movt r0, #29646 ; 0x73ce
+; ARM32: sxth r0, r0
+
+define internal i32 @trunc64To32Unsigned(i64 %padding, i64 %a) {
 entry:
   %conv = trunc i64 %a to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: trunc64To32Unsigned
-; CHECK: mov     eax,DWORD PTR [esp+0x4]
+; CHECK: mov     eax,DWORD PTR [esp+0xc]
 ;
 ; OPTM1-LABEL: trunc64To32Unsigned
 ; OPTM1: mov     eax,DWORD PTR [esp+
 
+; ARM32-LABEL: trunc64To32Unsigned
+; ARM32: mov r0, r2
+
 define internal i32 @trunc64To16Unsigned(i64 %a) {
 entry:
   %conv = trunc i64 %a to i16
   %conv.ret_ext = zext i16 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To16Unsigned
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK-NEXT: movzx  eax,ax
 ;
 ; OPTM1-LABEL: trunc64To16Unsigned
 ; OPTM1:      mov     eax,DWORD PTR [esp+
 ; OPTM1: movzx  eax,
 
+; ARM32-LABEL: trunc64To16Unsigned
+; ARM32: uxth
+
 define internal i32 @trunc64To8Unsigned(i64 %a) {
 entry:
   %conv = trunc i64 %a to i8
   %conv.ret_ext = zext i8 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To8Unsigned
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK-NEXT: movzx  eax,al
 ;
 ; OPTM1-LABEL: trunc64To8Unsigned
 ; OPTM1: mov    eax,DWORD PTR [esp+
 ; OPTM1: movzx  eax,
 
+; ARM32-LABEL: trunc64To8Unsigned
+; ARM32: uxtb
+
 define internal i32 @trunc64To1(i64 %a) {
 entry:
 ;  %tobool = icmp ne i64 %a, 0
   %tobool = trunc i64 %a to i1
   %tobool.ret_ext = zext i1 %tobool to i32
   ret i32 %tobool.ret_ext
 }
 ; CHECK-LABEL: trunc64To1
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK:      and     eax,0x1
 ; CHECK:      and     eax,0x1
 ;
 ; OPTM1-LABEL: trunc64To1
 ; OPTM1:      mov     eax,DWORD PTR [esp+
 ; OPTM1:      and     eax,0x1
 ; OPTM1:      and     eax,0x1
 
+; ARM32-LABEL: trunc64To1
+; ARM32: and r0, r0, #1
+; ARM32: and r0, r0, #1
+
 define internal i64 @sext32To64(i32 %a) {
 entry:
   %conv = sext i32 %a to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext32To64
 ; CHECK: mov
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext32To64
 ; OPTM1: mov
 ; OPTM1: sar {{.*}},0x1f
 
+; ARM32-LABEL: sext32To64
+; ARM32: asr {{.*}}, #31
+
 define internal i64 @sext16To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i16
   %conv = sext i16 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext16To64
 ; CHECK: movsx
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext16To64
 ; OPTM1: movsx
 ; OPTM1: sar {{.*}},0x1f
 
+; ARM32-LABEL: sext16To64
+; ARM32: sxth
+; ARM32: asr {{.*}}, #31
+
 define internal i64 @sext8To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i8
   %conv = sext i8 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext8To64
 ; CHECK: movsx
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext8To64
 ; OPTM1: movsx
 ; OPTM1: sar {{.*}},0x1f
 
+; ARM32-LABEL: sext8To64
+; ARM32: sxtb
+; ARM32: asr {{.*}}, #31
+
 define internal i64 @sext1To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i1
   %conv = sext i1 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext1To64
 ; CHECK: mov
 ; CHECK: shl {{.*}},0x1f
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext1To64
 ; OPTM1: mov
 ; OPTM1: shl {{.*}},0x1f
 ; OPTM1: sar {{.*}},0x1f
 
+; ARM32-LABEL: sext1To64
+; ARM32: lsl {{.*}}, #31
+; ARM32: asr {{.*}}, #31
+
 define internal i64 @zext32To64(i32 %a) {
 entry:
   %conv = zext i32 %a to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext32To64
 ; CHECK: mov
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext32To64
 ; OPTM1: mov
 ; OPTM1: mov {{.*}},0x0
 
+; ARM32-LABEL: zext32To64
+; ARM32: mov {{.*}}, #0
+
 define internal i64 @zext16To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i16
   %conv = zext i16 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext16To64
 ; CHECK: movzx
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext16To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}},0x0
 
+; ARM32-LABEL: zext16To64
+; ARM32: uxth
+; ARM32: mov {{.*}}, #0
+
 define internal i64 @zext8To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i8
   %conv = zext i8 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext8To64
 ; CHECK: movzx
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext8To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}},0x0
 
+; ARM32-LABEL: zext8To64
+; ARM32: uxtb
+; ARM32: mov {{.*}}, #0
+
 define internal i64 @zext1To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i1
   %conv = zext i1 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext1To64
 ; CHECK: and {{.*}},0x1
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext1To64
 ; OPTM1: and {{.*}},0x1
 ; OPTM1: mov {{.*}},0x0
 
+; ARM32-LABEL: zext1To64
+; ARM32: and {{.*}}, #1
+; ARM32: mov {{.*}}, #0
+
 define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp eq i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ skipping 312 matching lines @@
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpEq64Bool
 ; CHECK: jne
 ; CHECK: je
 ;
 ; OPTM1-LABEL: icmpEq64Bool
 ; OPTM1: jne
 ; OPTM1: je
 
+; ARM32-LABEL: icmpEq64Bool
+; ARM32: moveq
+; ARM32: movne
+
 define internal i32 @icmpNe64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ne i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpNe64Bool
 ; CHECK: jne
 ; CHECK: jne
 ;
 ; OPTM1-LABEL: icmpNe64Bool
 ; OPTM1: jne
 ; OPTM1: jne
 
+; ARM32-LABEL: icmpNe64Bool
+; ARM32: movne
+; ARM32: moveq
+
 define internal i32 @icmpSgt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp sgt i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpSgt64Bool
 ; CHECK: cmp
 ; CHECK: jg
 ; CHECK: jl
 ; CHECK: cmp
 ; CHECK: ja
 ;
 ; OPTM1-LABEL: icmpSgt64Bool
 ; OPTM1: cmp
 ; OPTM1: jg
 ; OPTM1: jl
 ; OPTM1: cmp
 ; OPTM1: ja
 
+; ARM32-LABEL: icmpSgt64Bool
+; ARM32: cmp
+; ARM32: sbcs
+; ARM32: movlt
+; ARM32: movge
+
 define internal i32 @icmpUgt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ugt i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpUgt64Bool
 ; CHECK: cmp
 ; CHECK: ja
 ; CHECK: jb
 ; CHECK: cmp
 ; CHECK: ja
 ;
 ; OPTM1-LABEL: icmpUgt64Bool
 ; OPTM1: cmp
 ; OPTM1: ja
 ; OPTM1: jb
 ; OPTM1: cmp
 ; OPTM1: ja
 
+; ARM32-LABEL: icmpUgt64Bool
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: movhi
+; ARM32: movls
+
 define internal i32 @icmpSge64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp sge i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpSge64Bool
 ; CHECK: cmp
 ; CHECK: jg
 ; CHECK: jl
 ; CHECK: cmp
 ; CHECK: jae
 ;
 ; OPTM1-LABEL: icmpSge64Bool
 ; OPTM1: cmp
 ; OPTM1: jg
 ; OPTM1: jl
 ; OPTM1: cmp
 ; OPTM1: jae
 
+; ARM32-LABEL: icmpSge64Bool
+; ARM32: cmp
+; ARM32: sbcs
+; ARM32: movge
+; ARM32: movlt
+
 define internal i32 @icmpUge64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp uge i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpUge64Bool
 ; CHECK: cmp
 ; CHECK: ja
 ; CHECK: jb
 ; CHECK: cmp
 ; CHECK: jae
 ;
 ; OPTM1-LABEL: icmpUge64Bool
 ; OPTM1: cmp
 ; OPTM1: ja
 ; OPTM1: jb
 ; OPTM1: cmp
 ; OPTM1: jae
 
+; ARM32-LABEL: icmpUge64Bool
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: movcs
+; ARM32: movcc
+
 define internal i32 @icmpSlt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp slt i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpSlt64Bool
 ; CHECK: cmp
 ; CHECK: jl
 ; CHECK: jg
 ; CHECK: cmp
 ; CHECK: jb
 ;
 ; OPTM1-LABEL: icmpSlt64Bool
 ; OPTM1: cmp
 ; OPTM1: jl
 ; OPTM1: jg
 ; OPTM1: cmp
 ; OPTM1: jb
 
+; ARM32-LABEL: icmpSlt64Bool
+; ARM32: cmp
+; ARM32: sbcs
+; ARM32: movlt
+; ARM32: movge
+
 define internal i32 @icmpUlt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ult i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpUlt64Bool
 ; CHECK: cmp
 ; CHECK: jb
 ; CHECK: ja
 ; CHECK: cmp
 ; CHECK: jb
 ;
 ; OPTM1-LABEL: icmpUlt64Bool
 ; OPTM1: cmp
 ; OPTM1: jb
 ; OPTM1: ja
 ; OPTM1: cmp
 ; OPTM1: jb
 
+; ARM32-LABEL: icmpUlt64Bool
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: movcc
+; ARM32: movcs
+
 define internal i32 @icmpSle64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp sle i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpSle64Bool
 ; CHECK: cmp
 ; CHECK: jl
 ; CHECK: jg
 ; CHECK: cmp
 ; CHECK: jbe
 ;
 ; OPTM1-LABEL: icmpSle64Bool
 ; OPTM1: cmp
 ; OPTM1: jl
 ; OPTM1: jg
 ; OPTM1: cmp
 ; OPTM1: jbe
 
+; ARM32-LABEL: icmpSle64Bool
+; ARM32: cmp
+; ARM32: sbcs
+; ARM32: movge
+; ARM32: movlt
+
 define internal i32 @icmpUle64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ule i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpUle64Bool
 ; CHECK: cmp
 ; CHECK: jb
 ; CHECK: ja
 ; CHECK: cmp
 ; CHECK: jbe
 ;
 ; OPTM1-LABEL: icmpUle64Bool
 ; OPTM1: cmp
 ; OPTM1: jb
 ; OPTM1: ja
 ; OPTM1: cmp
 ; OPTM1: jbe
 
+; ARM32-LABEL: icmpUle64Bool
+; ARM32: cmp
+; ARM32: cmpeq
+; ARM32: movls
+; ARM32: movhi
+
 define internal i64 @load64(i32 %a) {
 entry:
   %__1 = inttoptr i32 %a to i64*
   %v0 = load i64, i64* %__1, align 1
   ret i64 %v0
 }
 ; CHECK-LABEL: load64
 ; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]]
 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]+0x4]
@@ skipping 170 matching lines @@
   ret void
 }
 ; The following checks are not strictly necessary since one of the RUN
 ; lines actually runs the output through the assembler.
 ; CHECK-LABEL: icmpLt64Imm
 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
 ; OPTM1-LABEL: icmpLt64Imm
 ; OPTM1-NOT: cmp 0x{{[0-9a-f]+}},
 ; ARM32-LABEL: icmpLt64Imm
 ; ARM32-NOT: cmp #{{[0-9a-f]+}},