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Side by Side Diff: tests_lit/llvm2ice_tests/64bit.pnacl.ll

Issue 1143323013: Subzero ARM32: Lower shift and zext, sext, and trunc. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: rename variable Created 5 years, 6 months ago
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1 ; This tries to be a comprehensive test of i64 operations, in 1 ; This tries to be a comprehensive test of i64 operations, in
2 ; particular the patterns for lowering i64 operations into constituent 2 ; particular the patterns for lowering i64 operations into constituent
3 ; i32 operations on x86-32. 3 ; i32 operations on x86-32.
4 4
5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
6 ; RUN: --target x8632 -i %s --args -O2 \ 6 ; RUN: --target x8632 -i %s --args -O2 \
7 ; RUN: | %if --need=target_X8632 --command FileCheck %s 7 ; RUN: | %if --need=target_X8632 --command FileCheck %s
8 8
9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
10 ; RUN: --target x8632 -i %s --args -Om1 \ 10 ; RUN: --target x8632 -i %s --args -Om1 \
(...skipping 322 matching lines...) Expand 10 before | Expand all | Expand 10 after
333 ; CHECK: shl e 333 ; CHECK: shl e
334 ; CHECK: test {{.*}},0x20 334 ; CHECK: test {{.*}},0x20
335 ; CHECK: je 335 ; CHECK: je
336 ; 336 ;
337 ; OPTM1-LABEL: shl64BitSigned 337 ; OPTM1-LABEL: shl64BitSigned
338 ; OPTM1: shld 338 ; OPTM1: shld
339 ; OPTM1: shl e 339 ; OPTM1: shl e
340 ; OPTM1: test {{.*}},0x20 340 ; OPTM1: test {{.*}},0x20
341 ; OPTM1: je 341 ; OPTM1: je
342 342
343 ; ARM32-LABEL: shl64BitSigned
344 ; ARM32: sub [[REG3:r.*]], [[REG2:r.*]], #32
345 ; ARM32: lsl [[REG1:r.*]], {{r.*}}, [[REG2]]
346 ; ARM32: orr [[REG1]], [[REG1]], [[REG0:r.*]], lsl [[REG3]]
347 ; ARM32: rsb [[REG4:r.*]], [[REG2]], #32
348 ; ARM32: orr [[REG1]], [[REG1]], [[REG0]], lsr [[REG4]]
349 ; ARM32: lsl {{.*}}, [[REG0]], [[REG2]]
350
343 define internal i32 @shl64BitSignedTrunc(i64 %a, i64 %b) { 351 define internal i32 @shl64BitSignedTrunc(i64 %a, i64 %b) {
344 entry: 352 entry:
345 %shl = shl i64 %a, %b 353 %shl = shl i64 %a, %b
346 %result = trunc i64 %shl to i32 354 %result = trunc i64 %shl to i32
347 ret i32 %result 355 ret i32 %result
348 } 356 }
349 ; CHECK-LABEL: shl64BitSignedTrunc 357 ; CHECK-LABEL: shl64BitSignedTrunc
350 ; CHECK: mov 358 ; CHECK: mov
351 ; CHECK: shl e 359 ; CHECK: shl e
352 ; CHECK: test {{.*}},0x20 360 ; CHECK: test {{.*}},0x20
353 ; CHECK: je 361 ; CHECK: je
354 ; 362 ;
355 ; OPTM1-LABEL: shl64BitSignedTrunc 363 ; OPTM1-LABEL: shl64BitSignedTrunc
356 ; OPTM1: shld 364 ; OPTM1: shld
357 ; OPTM1: shl e 365 ; OPTM1: shl e
358 ; OPTM1: test {{.*}},0x20 366 ; OPTM1: test {{.*}},0x20
359 ; OPTM1: je 367 ; OPTM1: je
360 368
369 ; ARM32-LABEL: shl64BitSignedTrunc
370 ; ARM32: lsl r
371
361 define internal i64 @shl64BitUnsigned(i64 %a, i64 %b) { 372 define internal i64 @shl64BitUnsigned(i64 %a, i64 %b) {
362 entry: 373 entry:
363 %shl = shl i64 %a, %b 374 %shl = shl i64 %a, %b
364 ret i64 %shl 375 ret i64 %shl
365 } 376 }
366 ; CHECK-LABEL: shl64BitUnsigned 377 ; CHECK-LABEL: shl64BitUnsigned
367 ; CHECK: shld 378 ; CHECK: shld
368 ; CHECK: shl e 379 ; CHECK: shl e
369 ; CHECK: test {{.*}},0x20 380 ; CHECK: test {{.*}},0x20
370 ; CHECK: je 381 ; CHECK: je
371 ; 382 ;
372 ; OPTM1-LABEL: shl64BitUnsigned 383 ; OPTM1-LABEL: shl64BitUnsigned
373 ; OPTM1: shld 384 ; OPTM1: shld
374 ; OPTM1: shl e 385 ; OPTM1: shl e
375 ; OPTM1: test {{.*}},0x20 386 ; OPTM1: test {{.*}},0x20
376 ; OPTM1: je 387 ; OPTM1: je
377 388
389 ; ARM32-LABEL: shl64BitUnsigned
390 ; ARM32: sub
391 ; ARM32: lsl
392 ; ARM32: orr
393 ; ARM32: rsb
394 ; ARM32: orr
395 ; ARM32: lsl
396
378 define internal i64 @shr64BitSigned(i64 %a, i64 %b) { 397 define internal i64 @shr64BitSigned(i64 %a, i64 %b) {
379 entry: 398 entry:
380 %shr = ashr i64 %a, %b 399 %shr = ashr i64 %a, %b
381 ret i64 %shr 400 ret i64 %shr
382 } 401 }
383 ; CHECK-LABEL: shr64BitSigned 402 ; CHECK-LABEL: shr64BitSigned
384 ; CHECK: shrd 403 ; CHECK: shrd
385 ; CHECK: sar 404 ; CHECK: sar
386 ; CHECK: test {{.*}},0x20 405 ; CHECK: test {{.*}},0x20
387 ; CHECK: je 406 ; CHECK: je
388 ; CHECK: sar {{.*}},0x1f 407 ; CHECK: sar {{.*}},0x1f
389 ; 408 ;
390 ; OPTM1-LABEL: shr64BitSigned 409 ; OPTM1-LABEL: shr64BitSigned
391 ; OPTM1: shrd 410 ; OPTM1: shrd
392 ; OPTM1: sar 411 ; OPTM1: sar
393 ; OPTM1: test {{.*}},0x20 412 ; OPTM1: test {{.*}},0x20
394 ; OPTM1: je 413 ; OPTM1: je
395 ; OPTM1: sar {{.*}},0x1f 414 ; OPTM1: sar {{.*}},0x1f
396 415
416 ; ARM32-LABEL: shr64BitSigned
417 ; ARM32: rsb
418 ; ARM32: lsr
419 ; ARM32: orr
420 ; ARM32: subs
421 ; ARM32: orrpl
422 ; ARM32: asr
423
397 define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) { 424 define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) {
398 entry: 425 entry:
399 %shr = ashr i64 %a, %b 426 %shr = ashr i64 %a, %b
400 %result = trunc i64 %shr to i32 427 %result = trunc i64 %shr to i32
401 ret i32 %result 428 ret i32 %result
402 } 429 }
403 ; CHECK-LABEL: shr64BitSignedTrunc 430 ; CHECK-LABEL: shr64BitSignedTrunc
404 ; CHECK: shrd 431 ; CHECK: shrd
405 ; CHECK: sar 432 ; CHECK: sar
406 ; CHECK: test {{.*}},0x20 433 ; CHECK: test {{.*}},0x20
407 ; CHECK: je 434 ; CHECK: je
408 ; 435 ;
409 ; OPTM1-LABEL: shr64BitSignedTrunc 436 ; OPTM1-LABEL: shr64BitSignedTrunc
410 ; OPTM1: shrd 437 ; OPTM1: shrd
411 ; OPTM1: sar 438 ; OPTM1: sar
412 ; OPTM1: test {{.*}},0x20 439 ; OPTM1: test {{.*}},0x20
413 ; OPTM1: je 440 ; OPTM1: je
414 ; OPTM1: sar {{.*}},0x1f 441 ; OPTM1: sar {{.*}},0x1f
415 442
443 ; ARM32-LABEL: shr64BitSignedTrunc
444 ; ARM32: rsb
445 ; ARM32: lsr
446 ; ARM32: orr
447 ; ARM32: subs
448 ; ARM32: orrpl
449
416 define internal i64 @shr64BitUnsigned(i64 %a, i64 %b) { 450 define internal i64 @shr64BitUnsigned(i64 %a, i64 %b) {
417 entry: 451 entry:
418 %shr = lshr i64 %a, %b 452 %shr = lshr i64 %a, %b
419 ret i64 %shr 453 ret i64 %shr
420 } 454 }
421 ; CHECK-LABEL: shr64BitUnsigned 455 ; CHECK-LABEL: shr64BitUnsigned
422 ; CHECK: shrd 456 ; CHECK: shrd
423 ; CHECK: shr 457 ; CHECK: shr
424 ; CHECK: test {{.*}},0x20 458 ; CHECK: test {{.*}},0x20
425 ; CHECK: je 459 ; CHECK: je
426 ; 460 ;
427 ; OPTM1-LABEL: shr64BitUnsigned 461 ; OPTM1-LABEL: shr64BitUnsigned
428 ; OPTM1: shrd 462 ; OPTM1: shrd
429 ; OPTM1: shr 463 ; OPTM1: shr
430 ; OPTM1: test {{.*}},0x20 464 ; OPTM1: test {{.*}},0x20
431 ; OPTM1: je 465 ; OPTM1: je
432 466
467 ; ARM32-LABEL: shr64BitUnsigned
468 ; ARM32: rsb
469 ; ARM32: lsr
470 ; ARM32: orr
471 ; ARM32: sub
472 ; ARM32: orr
473 ; ARM32: lsr
474
433 define internal i32 @shr64BitUnsignedTrunc(i64 %a, i64 %b) { 475 define internal i32 @shr64BitUnsignedTrunc(i64 %a, i64 %b) {
434 entry: 476 entry:
435 %shr = lshr i64 %a, %b 477 %shr = lshr i64 %a, %b
436 %result = trunc i64 %shr to i32 478 %result = trunc i64 %shr to i32
437 ret i32 %result 479 ret i32 %result
438 } 480 }
439 ; CHECK-LABEL: shr64BitUnsignedTrunc 481 ; CHECK-LABEL: shr64BitUnsignedTrunc
440 ; CHECK: shrd 482 ; CHECK: shrd
441 ; CHECK: shr 483 ; CHECK: shr
442 ; CHECK: test {{.*}},0x20 484 ; CHECK: test {{.*}},0x20
443 ; CHECK: je 485 ; CHECK: je
444 ; 486 ;
445 ; OPTM1-LABEL: shr64BitUnsignedTrunc 487 ; OPTM1-LABEL: shr64BitUnsignedTrunc
446 ; OPTM1: shrd 488 ; OPTM1: shrd
447 ; OPTM1: shr 489 ; OPTM1: shr
448 ; OPTM1: test {{.*}},0x20 490 ; OPTM1: test {{.*}},0x20
449 ; OPTM1: je 491 ; OPTM1: je
450 492
493 ; ARM32-LABEL: shr64BitUnsignedTrunc
494 ; ARM32: rsb
495 ; ARM32: lsr
496 ; ARM32: orr
497 ; ARM32: sub
498 ; ARM32: orr
499
451 define internal i64 @and64BitSigned(i64 %a, i64 %b) { 500 define internal i64 @and64BitSigned(i64 %a, i64 %b) {
452 entry: 501 entry:
453 %and = and i64 %b, %a 502 %and = and i64 %b, %a
454 ret i64 %and 503 ret i64 %and
455 } 504 }
456 ; CHECK-LABEL: and64BitSigned 505 ; CHECK-LABEL: and64BitSigned
457 ; CHECK: and 506 ; CHECK: and
458 ; CHECK: and 507 ; CHECK: and
459 ; 508 ;
460 ; OPTM1-LABEL: and64BitSigned 509 ; OPTM1-LABEL: and64BitSigned
(...skipping 82 matching lines...) Expand 10 before | Expand all | Expand 10 after
543 ; CHECK: xor 592 ; CHECK: xor
544 ; 593 ;
545 ; OPTM1-LABEL: xor64BitUnsigned 594 ; OPTM1-LABEL: xor64BitUnsigned
546 ; OPTM1: xor 595 ; OPTM1: xor
547 ; OPTM1: xor 596 ; OPTM1: xor
548 597
549 ; ARM32-LABEL: xor64BitUnsigned 598 ; ARM32-LABEL: xor64BitUnsigned
550 ; ARM32: eor 599 ; ARM32: eor
551 ; ARM32: eor 600 ; ARM32: eor
552 601
553 define internal i32 @trunc64To32Signed(i64 %a) { 602 define internal i32 @trunc64To32Signed(i64 %padding, i64 %a) {
554 entry: 603 entry:
555 %conv = trunc i64 %a to i32 604 %conv = trunc i64 %a to i32
556 ret i32 %conv 605 ret i32 %conv
557 } 606 }
558 ; CHECK-LABEL: trunc64To32Signed 607 ; CHECK-LABEL: trunc64To32Signed
559 ; CHECK: mov eax,DWORD PTR [esp+0x4] 608 ; CHECK: mov eax,DWORD PTR [esp+0xc]
560 ; 609 ;
561 ; OPTM1-LABEL: trunc64To32Signed 610 ; OPTM1-LABEL: trunc64To32Signed
562 ; OPTM1: mov eax,DWORD PTR [esp+ 611 ; OPTM1: mov eax,DWORD PTR [esp+
563 612
613 ; ARM32-LABEL: trunc64To32Signed
614 ; ARM32: mov r0, r2
615
564 define internal i32 @trunc64To16Signed(i64 %a) { 616 define internal i32 @trunc64To16Signed(i64 %a) {
565 entry: 617 entry:
566 %conv = trunc i64 %a to i16 618 %conv = trunc i64 %a to i16
567 %conv.ret_ext = sext i16 %conv to i32 619 %conv.ret_ext = sext i16 %conv to i32
568 ret i32 %conv.ret_ext 620 ret i32 %conv.ret_ext
569 } 621 }
570 ; CHECK-LABEL: trunc64To16Signed 622 ; CHECK-LABEL: trunc64To16Signed
571 ; CHECK: mov eax,DWORD PTR [esp+0x4] 623 ; CHECK: mov eax,DWORD PTR [esp+0x4]
572 ; CHECK-NEXT: movsx eax,ax 624 ; CHECK-NEXT: movsx eax,ax
573 ; 625 ;
574 ; OPTM1-LABEL: trunc64To16Signed 626 ; OPTM1-LABEL: trunc64To16Signed
575 ; OPTM1: mov eax,DWORD PTR [esp+ 627 ; OPTM1: mov eax,DWORD PTR [esp+
576 ; OPTM1: movsx eax, 628 ; OPTM1: movsx eax,
577 629
630 ; ARM32-LABEL: trunc64To16Signed
631 ; ARM32: sxth r0, r0
632
578 define internal i32 @trunc64To8Signed(i64 %a) { 633 define internal i32 @trunc64To8Signed(i64 %a) {
579 entry: 634 entry:
580 %conv = trunc i64 %a to i8 635 %conv = trunc i64 %a to i8
581 %conv.ret_ext = sext i8 %conv to i32 636 %conv.ret_ext = sext i8 %conv to i32
582 ret i32 %conv.ret_ext 637 ret i32 %conv.ret_ext
583 } 638 }
584 ; CHECK-LABEL: trunc64To8Signed 639 ; CHECK-LABEL: trunc64To8Signed
585 ; CHECK: mov eax,DWORD PTR [esp+0x4] 640 ; CHECK: mov eax,DWORD PTR [esp+0x4]
586 ; CHECK-NEXT: movsx eax,al 641 ; CHECK-NEXT: movsx eax,al
587 ; 642 ;
588 ; OPTM1-LABEL: trunc64To8Signed 643 ; OPTM1-LABEL: trunc64To8Signed
589 ; OPTM1: mov eax,DWORD PTR [esp+ 644 ; OPTM1: mov eax,DWORD PTR [esp+
590 ; OPTM1: movsx eax, 645 ; OPTM1: movsx eax,
591 646
647 ; ARM32-LABEL: trunc64To8Signed
648 ; ARM32: sxtb r0, r0
649
592 define internal i32 @trunc64To32SignedConst() { 650 define internal i32 @trunc64To32SignedConst() {
593 entry: 651 entry:
594 %conv = trunc i64 12345678901234 to i32 652 %conv = trunc i64 12345678901234 to i32
595 ret i32 %conv 653 ret i32 %conv
596 } 654 }
597 ; CHECK-LABEL: trunc64To32SignedConst 655 ; CHECK-LABEL: trunc64To32SignedConst
598 ; CHECK: mov eax,0x73ce2ff2 656 ; CHECK: mov eax,0x73ce2ff2
599 ; 657 ;
600 ; OPTM1-LABEL: trunc64To32SignedConst 658 ; OPTM1-LABEL: trunc64To32SignedConst
601 ; OPTM1: mov eax,0x73ce2ff2 659 ; OPTM1: mov eax,0x73ce2ff2
602 660
661 ; ARM32-LABEL: trunc64To32SignedConst
662 ; ARM32: movw r0, #12274 ; 0x2ff2
663 ; ARM32: movt r0, #29646 ; 0x73ce
664
603 define internal i32 @trunc64To16SignedConst() { 665 define internal i32 @trunc64To16SignedConst() {
604 entry: 666 entry:
605 %conv = trunc i64 12345678901234 to i16 667 %conv = trunc i64 12345678901234 to i16
606 %conv.ret_ext = sext i16 %conv to i32 668 %conv.ret_ext = sext i16 %conv to i32
607 ret i32 %conv.ret_ext 669 ret i32 %conv.ret_ext
608 } 670 }
609 ; CHECK-LABEL: trunc64To16SignedConst 671 ; CHECK-LABEL: trunc64To16SignedConst
610 ; CHECK: mov eax,0x73ce2ff2 672 ; CHECK: mov eax,0x73ce2ff2
611 ; CHECK: movsx eax,ax 673 ; CHECK: movsx eax,ax
612 ; 674 ;
613 ; OPTM1-LABEL: trunc64To16SignedConst 675 ; OPTM1-LABEL: trunc64To16SignedConst
614 ; OPTM1: mov eax,0x73ce2ff2 676 ; OPTM1: mov eax,0x73ce2ff2
615 ; OPTM1: movsx eax, 677 ; OPTM1: movsx eax,
616 678
617 define internal i32 @trunc64To32Unsigned(i64 %a) { 679 ; ARM32-LABEL: trunc64To16SignedConst
680 ; ARM32: movw r0, #12274 ; 0x2ff2
681 ; ARM32: movt r0, #29646 ; 0x73ce
682 ; ARM32: sxth r0, r0
683
684 define internal i32 @trunc64To32Unsigned(i64 %padding, i64 %a) {
618 entry: 685 entry:
619 %conv = trunc i64 %a to i32 686 %conv = trunc i64 %a to i32
620 ret i32 %conv 687 ret i32 %conv
621 } 688 }
622 ; CHECK-LABEL: trunc64To32Unsigned 689 ; CHECK-LABEL: trunc64To32Unsigned
623 ; CHECK: mov eax,DWORD PTR [esp+0x4] 690 ; CHECK: mov eax,DWORD PTR [esp+0xc]
624 ; 691 ;
625 ; OPTM1-LABEL: trunc64To32Unsigned 692 ; OPTM1-LABEL: trunc64To32Unsigned
626 ; OPTM1: mov eax,DWORD PTR [esp+ 693 ; OPTM1: mov eax,DWORD PTR [esp+
627 694
695 ; ARM32-LABEL: trunc64To32Unsigned
696 ; ARM32: mov r0, r2
697
628 define internal i32 @trunc64To16Unsigned(i64 %a) { 698 define internal i32 @trunc64To16Unsigned(i64 %a) {
629 entry: 699 entry:
630 %conv = trunc i64 %a to i16 700 %conv = trunc i64 %a to i16
631 %conv.ret_ext = zext i16 %conv to i32 701 %conv.ret_ext = zext i16 %conv to i32
632 ret i32 %conv.ret_ext 702 ret i32 %conv.ret_ext
633 } 703 }
634 ; CHECK-LABEL: trunc64To16Unsigned 704 ; CHECK-LABEL: trunc64To16Unsigned
635 ; CHECK: mov eax,DWORD PTR [esp+0x4] 705 ; CHECK: mov eax,DWORD PTR [esp+0x4]
636 ; CHECK-NEXT: movzx eax,ax 706 ; CHECK-NEXT: movzx eax,ax
637 ; 707 ;
638 ; OPTM1-LABEL: trunc64To16Unsigned 708 ; OPTM1-LABEL: trunc64To16Unsigned
639 ; OPTM1: mov eax,DWORD PTR [esp+ 709 ; OPTM1: mov eax,DWORD PTR [esp+
640 ; OPTM1: movzx eax, 710 ; OPTM1: movzx eax,
641 711
712 ; ARM32-LABEL: trunc64To16Unsigned
713 ; ARM32: uxth
714
642 define internal i32 @trunc64To8Unsigned(i64 %a) { 715 define internal i32 @trunc64To8Unsigned(i64 %a) {
643 entry: 716 entry:
644 %conv = trunc i64 %a to i8 717 %conv = trunc i64 %a to i8
645 %conv.ret_ext = zext i8 %conv to i32 718 %conv.ret_ext = zext i8 %conv to i32
646 ret i32 %conv.ret_ext 719 ret i32 %conv.ret_ext
647 } 720 }
648 ; CHECK-LABEL: trunc64To8Unsigned 721 ; CHECK-LABEL: trunc64To8Unsigned
649 ; CHECK: mov eax,DWORD PTR [esp+0x4] 722 ; CHECK: mov eax,DWORD PTR [esp+0x4]
650 ; CHECK-NEXT: movzx eax,al 723 ; CHECK-NEXT: movzx eax,al
651 ; 724 ;
652 ; OPTM1-LABEL: trunc64To8Unsigned 725 ; OPTM1-LABEL: trunc64To8Unsigned
653 ; OPTM1: mov eax,DWORD PTR [esp+ 726 ; OPTM1: mov eax,DWORD PTR [esp+
654 ; OPTM1: movzx eax, 727 ; OPTM1: movzx eax,
655 728
729 ; ARM32-LABEL: trunc64To8Unsigned
730 ; ARM32: uxtb
731
656 define internal i32 @trunc64To1(i64 %a) { 732 define internal i32 @trunc64To1(i64 %a) {
657 entry: 733 entry:
658 ; %tobool = icmp ne i64 %a, 0 734 ; %tobool = icmp ne i64 %a, 0
659 %tobool = trunc i64 %a to i1 735 %tobool = trunc i64 %a to i1
660 %tobool.ret_ext = zext i1 %tobool to i32 736 %tobool.ret_ext = zext i1 %tobool to i32
661 ret i32 %tobool.ret_ext 737 ret i32 %tobool.ret_ext
662 } 738 }
663 ; CHECK-LABEL: trunc64To1 739 ; CHECK-LABEL: trunc64To1
664 ; CHECK: mov eax,DWORD PTR [esp+0x4] 740 ; CHECK: mov eax,DWORD PTR [esp+0x4]
665 ; CHECK: and eax,0x1 741 ; CHECK: and eax,0x1
666 ; CHECK: and eax,0x1 742 ; CHECK: and eax,0x1
667 ; 743 ;
668 ; OPTM1-LABEL: trunc64To1 744 ; OPTM1-LABEL: trunc64To1
669 ; OPTM1: mov eax,DWORD PTR [esp+ 745 ; OPTM1: mov eax,DWORD PTR [esp+
670 ; OPTM1: and eax,0x1 746 ; OPTM1: and eax,0x1
671 ; OPTM1: and eax,0x1 747 ; OPTM1: and eax,0x1
672 748
749 ; ARM32-LABEL: trunc64To1
750 ; ARM32: and r0, r0, #1
751 ; ARM32: and r0, r0, #1
752
673 define internal i64 @sext32To64(i32 %a) { 753 define internal i64 @sext32To64(i32 %a) {
674 entry: 754 entry:
675 %conv = sext i32 %a to i64 755 %conv = sext i32 %a to i64
676 ret i64 %conv 756 ret i64 %conv
677 } 757 }
678 ; CHECK-LABEL: sext32To64 758 ; CHECK-LABEL: sext32To64
679 ; CHECK: mov 759 ; CHECK: mov
680 ; CHECK: sar {{.*}},0x1f 760 ; CHECK: sar {{.*}},0x1f
681 ; 761 ;
682 ; OPTM1-LABEL: sext32To64 762 ; OPTM1-LABEL: sext32To64
683 ; OPTM1: mov 763 ; OPTM1: mov
684 ; OPTM1: sar {{.*}},0x1f 764 ; OPTM1: sar {{.*}},0x1f
685 765
766 ; ARM32-LABEL: sext32To64
767 ; ARM32: asr {{.*}}, #31
768
686 define internal i64 @sext16To64(i32 %a) { 769 define internal i64 @sext16To64(i32 %a) {
687 entry: 770 entry:
688 %a.arg_trunc = trunc i32 %a to i16 771 %a.arg_trunc = trunc i32 %a to i16
689 %conv = sext i16 %a.arg_trunc to i64 772 %conv = sext i16 %a.arg_trunc to i64
690 ret i64 %conv 773 ret i64 %conv
691 } 774 }
692 ; CHECK-LABEL: sext16To64 775 ; CHECK-LABEL: sext16To64
693 ; CHECK: movsx 776 ; CHECK: movsx
694 ; CHECK: sar {{.*}},0x1f 777 ; CHECK: sar {{.*}},0x1f
695 ; 778 ;
696 ; OPTM1-LABEL: sext16To64 779 ; OPTM1-LABEL: sext16To64
697 ; OPTM1: movsx 780 ; OPTM1: movsx
698 ; OPTM1: sar {{.*}},0x1f 781 ; OPTM1: sar {{.*}},0x1f
699 782
783 ; ARM32-LABEL: sext16To64
784 ; ARM32: sxth
785 ; ARM32: asr {{.*}}, #31
786
700 define internal i64 @sext8To64(i32 %a) { 787 define internal i64 @sext8To64(i32 %a) {
701 entry: 788 entry:
702 %a.arg_trunc = trunc i32 %a to i8 789 %a.arg_trunc = trunc i32 %a to i8
703 %conv = sext i8 %a.arg_trunc to i64 790 %conv = sext i8 %a.arg_trunc to i64
704 ret i64 %conv 791 ret i64 %conv
705 } 792 }
706 ; CHECK-LABEL: sext8To64 793 ; CHECK-LABEL: sext8To64
707 ; CHECK: movsx 794 ; CHECK: movsx
708 ; CHECK: sar {{.*}},0x1f 795 ; CHECK: sar {{.*}},0x1f
709 ; 796 ;
710 ; OPTM1-LABEL: sext8To64 797 ; OPTM1-LABEL: sext8To64
711 ; OPTM1: movsx 798 ; OPTM1: movsx
712 ; OPTM1: sar {{.*}},0x1f 799 ; OPTM1: sar {{.*}},0x1f
713 800
801 ; ARM32-LABEL: sext8To64
802 ; ARM32: sxtb
803 ; ARM32: asr {{.*}}, #31
804
714 define internal i64 @sext1To64(i32 %a) { 805 define internal i64 @sext1To64(i32 %a) {
715 entry: 806 entry:
716 %a.arg_trunc = trunc i32 %a to i1 807 %a.arg_trunc = trunc i32 %a to i1
717 %conv = sext i1 %a.arg_trunc to i64 808 %conv = sext i1 %a.arg_trunc to i64
718 ret i64 %conv 809 ret i64 %conv
719 } 810 }
720 ; CHECK-LABEL: sext1To64 811 ; CHECK-LABEL: sext1To64
721 ; CHECK: mov 812 ; CHECK: mov
722 ; CHECK: shl {{.*}},0x1f 813 ; CHECK: shl {{.*}},0x1f
723 ; CHECK: sar {{.*}},0x1f 814 ; CHECK: sar {{.*}},0x1f
724 ; 815 ;
725 ; OPTM1-LABEL: sext1To64 816 ; OPTM1-LABEL: sext1To64
726 ; OPTM1: mov 817 ; OPTM1: mov
727 ; OPTM1: shl {{.*}},0x1f 818 ; OPTM1: shl {{.*}},0x1f
728 ; OPTM1: sar {{.*}},0x1f 819 ; OPTM1: sar {{.*}},0x1f
729 820
821 ; ARM32-LABEL: sext1To64
822 ; ARM32: lsl {{.*}}, #31
823 ; ARM32: asr {{.*}}, #31
824
730 define internal i64 @zext32To64(i32 %a) { 825 define internal i64 @zext32To64(i32 %a) {
731 entry: 826 entry:
732 %conv = zext i32 %a to i64 827 %conv = zext i32 %a to i64
733 ret i64 %conv 828 ret i64 %conv
734 } 829 }
735 ; CHECK-LABEL: zext32To64 830 ; CHECK-LABEL: zext32To64
736 ; CHECK: mov 831 ; CHECK: mov
737 ; CHECK: mov {{.*}},0x0 832 ; CHECK: mov {{.*}},0x0
738 ; 833 ;
739 ; OPTM1-LABEL: zext32To64 834 ; OPTM1-LABEL: zext32To64
740 ; OPTM1: mov 835 ; OPTM1: mov
741 ; OPTM1: mov {{.*}},0x0 836 ; OPTM1: mov {{.*}},0x0
742 837
838 ; ARM32-LABEL: zext32To64
839 ; ARM32: mov {{.*}}, #0
840
743 define internal i64 @zext16To64(i32 %a) { 841 define internal i64 @zext16To64(i32 %a) {
744 entry: 842 entry:
745 %a.arg_trunc = trunc i32 %a to i16 843 %a.arg_trunc = trunc i32 %a to i16
746 %conv = zext i16 %a.arg_trunc to i64 844 %conv = zext i16 %a.arg_trunc to i64
747 ret i64 %conv 845 ret i64 %conv
748 } 846 }
749 ; CHECK-LABEL: zext16To64 847 ; CHECK-LABEL: zext16To64
750 ; CHECK: movzx 848 ; CHECK: movzx
751 ; CHECK: mov {{.*}},0x0 849 ; CHECK: mov {{.*}},0x0
752 ; 850 ;
753 ; OPTM1-LABEL: zext16To64 851 ; OPTM1-LABEL: zext16To64
754 ; OPTM1: movzx 852 ; OPTM1: movzx
755 ; OPTM1: mov {{.*}},0x0 853 ; OPTM1: mov {{.*}},0x0
756 854
855 ; ARM32-LABEL: zext16To64
856 ; ARM32: uxth
857 ; ARM32: mov {{.*}}, #0
858
757 define internal i64 @zext8To64(i32 %a) { 859 define internal i64 @zext8To64(i32 %a) {
758 entry: 860 entry:
759 %a.arg_trunc = trunc i32 %a to i8 861 %a.arg_trunc = trunc i32 %a to i8
760 %conv = zext i8 %a.arg_trunc to i64 862 %conv = zext i8 %a.arg_trunc to i64
761 ret i64 %conv 863 ret i64 %conv
762 } 864 }
763 ; CHECK-LABEL: zext8To64 865 ; CHECK-LABEL: zext8To64
764 ; CHECK: movzx 866 ; CHECK: movzx
765 ; CHECK: mov {{.*}},0x0 867 ; CHECK: mov {{.*}},0x0
766 ; 868 ;
767 ; OPTM1-LABEL: zext8To64 869 ; OPTM1-LABEL: zext8To64
768 ; OPTM1: movzx 870 ; OPTM1: movzx
769 ; OPTM1: mov {{.*}},0x0 871 ; OPTM1: mov {{.*}},0x0
770 872
873 ; ARM32-LABEL: zext8To64
874 ; ARM32: uxtb
875 ; ARM32: mov {{.*}}, #0
876
771 define internal i64 @zext1To64(i32 %a) { 877 define internal i64 @zext1To64(i32 %a) {
772 entry: 878 entry:
773 %a.arg_trunc = trunc i32 %a to i1 879 %a.arg_trunc = trunc i32 %a to i1
774 %conv = zext i1 %a.arg_trunc to i64 880 %conv = zext i1 %a.arg_trunc to i64
775 ret i64 %conv 881 ret i64 %conv
776 } 882 }
777 ; CHECK-LABEL: zext1To64 883 ; CHECK-LABEL: zext1To64
778 ; CHECK: and {{.*}},0x1 884 ; CHECK: and {{.*}},0x1
779 ; CHECK: mov {{.*}},0x0 885 ; CHECK: mov {{.*}},0x0
780 ; 886 ;
781 ; OPTM1-LABEL: zext1To64 887 ; OPTM1-LABEL: zext1To64
782 ; OPTM1: and {{.*}},0x1 888 ; OPTM1: and {{.*}},0x1
783 ; OPTM1: mov {{.*}},0x0 889 ; OPTM1: mov {{.*}},0x0
784 890
891 ; ARM32-LABEL: zext1To64
892 ; ARM32: and {{.*}}, #1
893 ; ARM32: mov {{.*}}, #0
894
785 define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) { 895 define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) {
786 entry: 896 entry:
787 %cmp = icmp eq i64 %a, %b 897 %cmp = icmp eq i64 %a, %b
788 br i1 %cmp, label %if.then, label %if.end 898 br i1 %cmp, label %if.then, label %if.end
789 899
790 if.then: ; preds = %entry 900 if.then: ; preds = %entry
791 call void @func() 901 call void @func()
792 br label %if.end 902 br label %if.end
793 903
794 if.end: ; preds = %if.then, %entry 904 if.end: ; preds = %if.then, %entry
(...skipping 312 matching lines...) Expand 10 before | Expand all | Expand 10 after
1107 ret i32 %cmp.ret_ext 1217 ret i32 %cmp.ret_ext
1108 } 1218 }
1109 ; CHECK-LABEL: icmpEq64Bool 1219 ; CHECK-LABEL: icmpEq64Bool
1110 ; CHECK: jne 1220 ; CHECK: jne
1111 ; CHECK: je 1221 ; CHECK: je
1112 ; 1222 ;
1113 ; OPTM1-LABEL: icmpEq64Bool 1223 ; OPTM1-LABEL: icmpEq64Bool
1114 ; OPTM1: jne 1224 ; OPTM1: jne
1115 ; OPTM1: je 1225 ; OPTM1: je
1116 1226
1227 ; ARM32-LABEL: icmpEq64Bool
1228 ; ARM32: moveq
1229 ; ARM32: movne
1230
1117 define internal i32 @icmpNe64Bool(i64 %a, i64 %b) { 1231 define internal i32 @icmpNe64Bool(i64 %a, i64 %b) {
1118 entry: 1232 entry:
1119 %cmp = icmp ne i64 %a, %b 1233 %cmp = icmp ne i64 %a, %b
1120 %cmp.ret_ext = zext i1 %cmp to i32 1234 %cmp.ret_ext = zext i1 %cmp to i32
1121 ret i32 %cmp.ret_ext 1235 ret i32 %cmp.ret_ext
1122 } 1236 }
1123 ; CHECK-LABEL: icmpNe64Bool 1237 ; CHECK-LABEL: icmpNe64Bool
1124 ; CHECK: jne 1238 ; CHECK: jne
1125 ; CHECK: jne 1239 ; CHECK: jne
1126 ; 1240 ;
1127 ; OPTM1-LABEL: icmpNe64Bool 1241 ; OPTM1-LABEL: icmpNe64Bool
1128 ; OPTM1: jne 1242 ; OPTM1: jne
1129 ; OPTM1: jne 1243 ; OPTM1: jne
1130 1244
1245 ; ARM32-LABEL: icmpNe64Bool
1246 ; ARM32: movne
1247 ; ARM32: moveq
1248
1131 define internal i32 @icmpSgt64Bool(i64 %a, i64 %b) { 1249 define internal i32 @icmpSgt64Bool(i64 %a, i64 %b) {
1132 entry: 1250 entry:
1133 %cmp = icmp sgt i64 %a, %b 1251 %cmp = icmp sgt i64 %a, %b
1134 %cmp.ret_ext = zext i1 %cmp to i32 1252 %cmp.ret_ext = zext i1 %cmp to i32
1135 ret i32 %cmp.ret_ext 1253 ret i32 %cmp.ret_ext
1136 } 1254 }
1137 ; CHECK-LABEL: icmpSgt64Bool 1255 ; CHECK-LABEL: icmpSgt64Bool
1138 ; CHECK: cmp 1256 ; CHECK: cmp
1139 ; CHECK: jg 1257 ; CHECK: jg
1140 ; CHECK: jl 1258 ; CHECK: jl
1141 ; CHECK: cmp 1259 ; CHECK: cmp
1142 ; CHECK: ja 1260 ; CHECK: ja
1143 ; 1261 ;
1144 ; OPTM1-LABEL: icmpSgt64Bool 1262 ; OPTM1-LABEL: icmpSgt64Bool
1145 ; OPTM1: cmp 1263 ; OPTM1: cmp
1146 ; OPTM1: jg 1264 ; OPTM1: jg
1147 ; OPTM1: jl 1265 ; OPTM1: jl
1148 ; OPTM1: cmp 1266 ; OPTM1: cmp
1149 ; OPTM1: ja 1267 ; OPTM1: ja
1150 1268
1269 ; ARM32-LABEL: icmpSgt64Bool
1270 ; ARM32: cmp
1271 ; ARM32: sbcs
1272 ; ARM32: movlt
1273 ; ARM32: movge
1274
1151 define internal i32 @icmpUgt64Bool(i64 %a, i64 %b) { 1275 define internal i32 @icmpUgt64Bool(i64 %a, i64 %b) {
1152 entry: 1276 entry:
1153 %cmp = icmp ugt i64 %a, %b 1277 %cmp = icmp ugt i64 %a, %b
1154 %cmp.ret_ext = zext i1 %cmp to i32 1278 %cmp.ret_ext = zext i1 %cmp to i32
1155 ret i32 %cmp.ret_ext 1279 ret i32 %cmp.ret_ext
1156 } 1280 }
1157 ; CHECK-LABEL: icmpUgt64Bool 1281 ; CHECK-LABEL: icmpUgt64Bool
1158 ; CHECK: cmp 1282 ; CHECK: cmp
1159 ; CHECK: ja 1283 ; CHECK: ja
1160 ; CHECK: jb 1284 ; CHECK: jb
1161 ; CHECK: cmp 1285 ; CHECK: cmp
1162 ; CHECK: ja 1286 ; CHECK: ja
1163 ; 1287 ;
1164 ; OPTM1-LABEL: icmpUgt64Bool 1288 ; OPTM1-LABEL: icmpUgt64Bool
1165 ; OPTM1: cmp 1289 ; OPTM1: cmp
1166 ; OPTM1: ja 1290 ; OPTM1: ja
1167 ; OPTM1: jb 1291 ; OPTM1: jb
1168 ; OPTM1: cmp 1292 ; OPTM1: cmp
1169 ; OPTM1: ja 1293 ; OPTM1: ja
1170 1294
1295 ; ARM32-LABEL: icmpUgt64Bool
1296 ; ARM32: cmp
1297 ; ARM32: cmpeq
1298 ; ARM32: movhi
1299 ; ARM32: movls
1300
1171 define internal i32 @icmpSge64Bool(i64 %a, i64 %b) { 1301 define internal i32 @icmpSge64Bool(i64 %a, i64 %b) {
1172 entry: 1302 entry:
1173 %cmp = icmp sge i64 %a, %b 1303 %cmp = icmp sge i64 %a, %b
1174 %cmp.ret_ext = zext i1 %cmp to i32 1304 %cmp.ret_ext = zext i1 %cmp to i32
1175 ret i32 %cmp.ret_ext 1305 ret i32 %cmp.ret_ext
1176 } 1306 }
1177 ; CHECK-LABEL: icmpSge64Bool 1307 ; CHECK-LABEL: icmpSge64Bool
1178 ; CHECK: cmp 1308 ; CHECK: cmp
1179 ; CHECK: jg 1309 ; CHECK: jg
1180 ; CHECK: jl 1310 ; CHECK: jl
1181 ; CHECK: cmp 1311 ; CHECK: cmp
1182 ; CHECK: jae 1312 ; CHECK: jae
1183 ; 1313 ;
1184 ; OPTM1-LABEL: icmpSge64Bool 1314 ; OPTM1-LABEL: icmpSge64Bool
1185 ; OPTM1: cmp 1315 ; OPTM1: cmp
1186 ; OPTM1: jg 1316 ; OPTM1: jg
1187 ; OPTM1: jl 1317 ; OPTM1: jl
1188 ; OPTM1: cmp 1318 ; OPTM1: cmp
1189 ; OPTM1: jae 1319 ; OPTM1: jae
1190 1320
1321 ; ARM32-LABEL: icmpSge64Bool
1322 ; ARM32: cmp
1323 ; ARM32: sbcs
1324 ; ARM32: movge
1325 ; ARM32: movlt
1326
1191 define internal i32 @icmpUge64Bool(i64 %a, i64 %b) { 1327 define internal i32 @icmpUge64Bool(i64 %a, i64 %b) {
1192 entry: 1328 entry:
1193 %cmp = icmp uge i64 %a, %b 1329 %cmp = icmp uge i64 %a, %b
1194 %cmp.ret_ext = zext i1 %cmp to i32 1330 %cmp.ret_ext = zext i1 %cmp to i32
1195 ret i32 %cmp.ret_ext 1331 ret i32 %cmp.ret_ext
1196 } 1332 }
1197 ; CHECK-LABEL: icmpUge64Bool 1333 ; CHECK-LABEL: icmpUge64Bool
1198 ; CHECK: cmp 1334 ; CHECK: cmp
1199 ; CHECK: ja 1335 ; CHECK: ja
1200 ; CHECK: jb 1336 ; CHECK: jb
1201 ; CHECK: cmp 1337 ; CHECK: cmp
1202 ; CHECK: jae 1338 ; CHECK: jae
1203 ; 1339 ;
1204 ; OPTM1-LABEL: icmpUge64Bool 1340 ; OPTM1-LABEL: icmpUge64Bool
1205 ; OPTM1: cmp 1341 ; OPTM1: cmp
1206 ; OPTM1: ja 1342 ; OPTM1: ja
1207 ; OPTM1: jb 1343 ; OPTM1: jb
1208 ; OPTM1: cmp 1344 ; OPTM1: cmp
1209 ; OPTM1: jae 1345 ; OPTM1: jae
1210 1346
1347 ; ARM32-LABEL: icmpUge64Bool
1348 ; ARM32: cmp
1349 ; ARM32: cmpeq
1350 ; ARM32: movcs
1351 ; ARM32: movcc
1352
1211 define internal i32 @icmpSlt64Bool(i64 %a, i64 %b) { 1353 define internal i32 @icmpSlt64Bool(i64 %a, i64 %b) {
1212 entry: 1354 entry:
1213 %cmp = icmp slt i64 %a, %b 1355 %cmp = icmp slt i64 %a, %b
1214 %cmp.ret_ext = zext i1 %cmp to i32 1356 %cmp.ret_ext = zext i1 %cmp to i32
1215 ret i32 %cmp.ret_ext 1357 ret i32 %cmp.ret_ext
1216 } 1358 }
1217 ; CHECK-LABEL: icmpSlt64Bool 1359 ; CHECK-LABEL: icmpSlt64Bool
1218 ; CHECK: cmp 1360 ; CHECK: cmp
1219 ; CHECK: jl 1361 ; CHECK: jl
1220 ; CHECK: jg 1362 ; CHECK: jg
1221 ; CHECK: cmp 1363 ; CHECK: cmp
1222 ; CHECK: jb 1364 ; CHECK: jb
1223 ; 1365 ;
1224 ; OPTM1-LABEL: icmpSlt64Bool 1366 ; OPTM1-LABEL: icmpSlt64Bool
1225 ; OPTM1: cmp 1367 ; OPTM1: cmp
1226 ; OPTM1: jl 1368 ; OPTM1: jl
1227 ; OPTM1: jg 1369 ; OPTM1: jg
1228 ; OPTM1: cmp 1370 ; OPTM1: cmp
1229 ; OPTM1: jb 1371 ; OPTM1: jb
1230 1372
1373 ; ARM32-LABEL: icmpSlt64Bool
1374 ; ARM32: cmp
1375 ; ARM32: sbcs
1376 ; ARM32: movlt
1377 ; ARM32: movge
1378
1231 define internal i32 @icmpUlt64Bool(i64 %a, i64 %b) { 1379 define internal i32 @icmpUlt64Bool(i64 %a, i64 %b) {
1232 entry: 1380 entry:
1233 %cmp = icmp ult i64 %a, %b 1381 %cmp = icmp ult i64 %a, %b
1234 %cmp.ret_ext = zext i1 %cmp to i32 1382 %cmp.ret_ext = zext i1 %cmp to i32
1235 ret i32 %cmp.ret_ext 1383 ret i32 %cmp.ret_ext
1236 } 1384 }
1237 ; CHECK-LABEL: icmpUlt64Bool 1385 ; CHECK-LABEL: icmpUlt64Bool
1238 ; CHECK: cmp 1386 ; CHECK: cmp
1239 ; CHECK: jb 1387 ; CHECK: jb
1240 ; CHECK: ja 1388 ; CHECK: ja
1241 ; CHECK: cmp 1389 ; CHECK: cmp
1242 ; CHECK: jb 1390 ; CHECK: jb
1243 ; 1391 ;
1244 ; OPTM1-LABEL: icmpUlt64Bool 1392 ; OPTM1-LABEL: icmpUlt64Bool
1245 ; OPTM1: cmp 1393 ; OPTM1: cmp
1246 ; OPTM1: jb 1394 ; OPTM1: jb
1247 ; OPTM1: ja 1395 ; OPTM1: ja
1248 ; OPTM1: cmp 1396 ; OPTM1: cmp
1249 ; OPTM1: jb 1397 ; OPTM1: jb
1250 1398
1399 ; ARM32-LABEL: icmpUlt64Bool
1400 ; ARM32: cmp
1401 ; ARM32: cmpeq
1402 ; ARM32: movcc
1403 ; ARM32: movcs
1404
1251 define internal i32 @icmpSle64Bool(i64 %a, i64 %b) { 1405 define internal i32 @icmpSle64Bool(i64 %a, i64 %b) {
1252 entry: 1406 entry:
1253 %cmp = icmp sle i64 %a, %b 1407 %cmp = icmp sle i64 %a, %b
1254 %cmp.ret_ext = zext i1 %cmp to i32 1408 %cmp.ret_ext = zext i1 %cmp to i32
1255 ret i32 %cmp.ret_ext 1409 ret i32 %cmp.ret_ext
1256 } 1410 }
1257 ; CHECK-LABEL: icmpSle64Bool 1411 ; CHECK-LABEL: icmpSle64Bool
1258 ; CHECK: cmp 1412 ; CHECK: cmp
1259 ; CHECK: jl 1413 ; CHECK: jl
1260 ; CHECK: jg 1414 ; CHECK: jg
1261 ; CHECK: cmp 1415 ; CHECK: cmp
1262 ; CHECK: jbe 1416 ; CHECK: jbe
1263 ; 1417 ;
1264 ; OPTM1-LABEL: icmpSle64Bool 1418 ; OPTM1-LABEL: icmpSle64Bool
1265 ; OPTM1: cmp 1419 ; OPTM1: cmp
1266 ; OPTM1: jl 1420 ; OPTM1: jl
1267 ; OPTM1: jg 1421 ; OPTM1: jg
1268 ; OPTM1: cmp 1422 ; OPTM1: cmp
1269 ; OPTM1: jbe 1423 ; OPTM1: jbe
1270 1424
1425 ; ARM32-LABEL: icmpSle64Bool
1426 ; ARM32: cmp
1427 ; ARM32: sbcs
1428 ; ARM32: movge
1429 ; ARM32: movlt
1430
1271 define internal i32 @icmpUle64Bool(i64 %a, i64 %b) { 1431 define internal i32 @icmpUle64Bool(i64 %a, i64 %b) {
1272 entry: 1432 entry:
1273 %cmp = icmp ule i64 %a, %b 1433 %cmp = icmp ule i64 %a, %b
1274 %cmp.ret_ext = zext i1 %cmp to i32 1434 %cmp.ret_ext = zext i1 %cmp to i32
1275 ret i32 %cmp.ret_ext 1435 ret i32 %cmp.ret_ext
1276 } 1436 }
1277 ; CHECK-LABEL: icmpUle64Bool 1437 ; CHECK-LABEL: icmpUle64Bool
1278 ; CHECK: cmp 1438 ; CHECK: cmp
1279 ; CHECK: jb 1439 ; CHECK: jb
1280 ; CHECK: ja 1440 ; CHECK: ja
1281 ; CHECK: cmp 1441 ; CHECK: cmp
1282 ; CHECK: jbe 1442 ; CHECK: jbe
1283 ; 1443 ;
1284 ; OPTM1-LABEL: icmpUle64Bool 1444 ; OPTM1-LABEL: icmpUle64Bool
1285 ; OPTM1: cmp 1445 ; OPTM1: cmp
1286 ; OPTM1: jb 1446 ; OPTM1: jb
1287 ; OPTM1: ja 1447 ; OPTM1: ja
1288 ; OPTM1: cmp 1448 ; OPTM1: cmp
1289 ; OPTM1: jbe 1449 ; OPTM1: jbe
1290 1450
1451 ; ARM32-LABEL: icmpUle64Bool
1452 ; ARM32: cmp
1453 ; ARM32: cmpeq
1454 ; ARM32: movls
1455 ; ARM32: movhi
1456
1291 define internal i64 @load64(i32 %a) { 1457 define internal i64 @load64(i32 %a) {
1292 entry: 1458 entry:
1293 %__1 = inttoptr i32 %a to i64* 1459 %__1 = inttoptr i32 %a to i64*
1294 %v0 = load i64, i64* %__1, align 1 1460 %v0 = load i64, i64* %__1, align 1
1295 ret i64 %v0 1461 ret i64 %v0
1296 } 1462 }
1297 ; CHECK-LABEL: load64 1463 ; CHECK-LABEL: load64
1298 ; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4] 1464 ; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
1299 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]] 1465 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]]
1300 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]+0x4] 1466 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]+0x4]
(...skipping 170 matching lines...) Expand 10 before | Expand all | Expand 10 after
1471 ret void 1637 ret void
1472 } 1638 }
1473 ; The following checks are not strictly necessary since one of the RUN 1639 ; The following checks are not strictly necessary since one of the RUN
1474 ; lines actually runs the output through the assembler. 1640 ; lines actually runs the output through the assembler.
1475 ; CHECK-LABEL: icmpLt64Imm 1641 ; CHECK-LABEL: icmpLt64Imm
1476 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}}, 1642 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
1477 ; OPTM1-LABEL: icmpLt64Imm 1643 ; OPTM1-LABEL: icmpLt64Imm
1478 ; OPTM1-NOT: cmp 0x{{[0-9a-f]+}}, 1644 ; OPTM1-NOT: cmp 0x{{[0-9a-f]+}},
1479 ; ARM32-LABEL: icmpLt64Imm 1645 ; ARM32-LABEL: icmpLt64Imm
1480 ; ARM32-NOT: cmp #{{[0-9a-f]+}}, 1646 ; ARM32-NOT: cmp #{{[0-9a-f]+}},
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