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Side by Side Diff: src/IceTargetLoweringARM32.h

Issue 1143323013: Subzero ARM32: Lower shift and zext, sext, and trunc. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: rename variable Created 5 years, 6 months ago
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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file declares the TargetLoweringARM32 class, which implements the 10 // This file declares the TargetLoweringARM32 class, which implements the
(...skipping 135 matching lines...) Expand 10 before | Expand all | Expand 10 after
146 InstARM32Add::create(Func, Dest, Src0, Src1, Pred, SetFlags)); 146 InstARM32Add::create(Func, Dest, Src0, Src1, Pred, SetFlags));
147 } 147 }
148 void _adc(Variable *Dest, Variable *Src0, Operand *Src1, 148 void _adc(Variable *Dest, Variable *Src0, Operand *Src1,
149 CondARM32::Cond Pred = CondARM32::AL) { 149 CondARM32::Cond Pred = CondARM32::AL) {
150 Context.insert(InstARM32Adc::create(Func, Dest, Src0, Src1, Pred)); 150 Context.insert(InstARM32Adc::create(Func, Dest, Src0, Src1, Pred));
151 } 151 }
152 void _and(Variable *Dest, Variable *Src0, Operand *Src1, 152 void _and(Variable *Dest, Variable *Src0, Operand *Src1,
153 CondARM32::Cond Pred = CondARM32::AL) { 153 CondARM32::Cond Pred = CondARM32::AL) {
154 Context.insert(InstARM32And::create(Func, Dest, Src0, Src1, Pred)); 154 Context.insert(InstARM32And::create(Func, Dest, Src0, Src1, Pred));
155 } 155 }
156 void _asr(Variable *Dest, Variable *Src0, Operand *Src1,
157 CondARM32::Cond Pred = CondARM32::AL) {
158 Context.insert(InstARM32Asr::create(Func, Dest, Src0, Src1, Pred));
159 }
156 void _bic(Variable *Dest, Variable *Src0, Operand *Src1, 160 void _bic(Variable *Dest, Variable *Src0, Operand *Src1,
157 CondARM32::Cond Pred = CondARM32::AL) { 161 CondARM32::Cond Pred = CondARM32::AL) {
158 Context.insert(InstARM32Bic::create(Func, Dest, Src0, Src1, Pred)); 162 Context.insert(InstARM32Bic::create(Func, Dest, Src0, Src1, Pred));
159 } 163 }
160 void _br(CondARM32::Cond Condition, CfgNode *TargetTrue, 164 void _br(CondARM32::Cond Condition, CfgNode *TargetTrue,
161 CfgNode *TargetFalse) { 165 CfgNode *TargetFalse) {
162 Context.insert( 166 Context.insert(
163 InstARM32Br::create(Func, TargetTrue, TargetFalse, Condition)); 167 InstARM32Br::create(Func, TargetTrue, TargetFalse, Condition));
164 } 168 }
165 void _br(CfgNode *Target) { 169 void _br(CfgNode *Target) {
166 Context.insert(InstARM32Br::create(Func, Target)); 170 Context.insert(InstARM32Br::create(Func, Target));
167 } 171 }
168 void _cmp(Variable *Src0, Operand *Src1, 172 void _cmp(Variable *Src0, Operand *Src1,
169 CondARM32::Cond Pred = CondARM32::AL) { 173 CondARM32::Cond Pred = CondARM32::AL) {
170 Context.insert(InstARM32Cmp::create(Func, Src0, Src1, Pred)); 174 Context.insert(InstARM32Cmp::create(Func, Src0, Src1, Pred));
171 } 175 }
172 void _eor(Variable *Dest, Variable *Src0, Operand *Src1, 176 void _eor(Variable *Dest, Variable *Src0, Operand *Src1,
173 CondARM32::Cond Pred = CondARM32::AL) { 177 CondARM32::Cond Pred = CondARM32::AL) {
174 Context.insert(InstARM32Eor::create(Func, Dest, Src0, Src1, Pred)); 178 Context.insert(InstARM32Eor::create(Func, Dest, Src0, Src1, Pred));
175 } 179 }
176 void _ldr(Variable *Dest, OperandARM32Mem *Addr, 180 void _ldr(Variable *Dest, OperandARM32Mem *Addr,
177 CondARM32::Cond Pred = CondARM32::AL) { 181 CondARM32::Cond Pred = CondARM32::AL) {
178 Context.insert(InstARM32Ldr::create(Func, Dest, Addr, Pred)); 182 Context.insert(InstARM32Ldr::create(Func, Dest, Addr, Pred));
179 } 183 }
180 void _lsl(Variable *Dest, Variable *Src0, Operand *Src1, 184 void _lsl(Variable *Dest, Variable *Src0, Operand *Src1,
181 CondARM32::Cond Pred = CondARM32::AL) { 185 CondARM32::Cond Pred = CondARM32::AL) {
182 Context.insert(InstARM32Lsl::create(Func, Dest, Src0, Src1, Pred)); 186 Context.insert(InstARM32Lsl::create(Func, Dest, Src0, Src1, Pred));
183 } 187 }
188 void _lsr(Variable *Dest, Variable *Src0, Operand *Src1,
189 CondARM32::Cond Pred = CondARM32::AL) {
190 Context.insert(InstARM32Lsr::create(Func, Dest, Src0, Src1, Pred));
191 }
184 void _mla(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc, 192 void _mla(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc,
185 CondARM32::Cond Pred = CondARM32::AL) { 193 CondARM32::Cond Pred = CondARM32::AL) {
186 Context.insert(InstARM32Mla::create(Func, Dest, Src0, Src1, Acc, Pred)); 194 Context.insert(InstARM32Mla::create(Func, Dest, Src0, Src1, Acc, Pred));
187 } 195 }
188 // If Dest=nullptr is passed in, then a new variable is created, 196 // If Dest=nullptr is passed in, then a new variable is created,
189 // marked as infinite register allocation weight, and returned 197 // marked as infinite register allocation weight, and returned
190 // through the in/out Dest argument. 198 // through the in/out Dest argument.
191 void _mov(Variable *&Dest, Operand *Src0, 199 void _mov(Variable *&Dest, Operand *Src0,
192 CondARM32::Cond Pred = CondARM32::AL, 200 CondARM32::Cond Pred = CondARM32::AL,
193 int32_t RegNum = Variable::NoRegister) { 201 int32_t RegNum = Variable::NoRegister) {
(...skipping 31 matching lines...) Expand 10 before | Expand all | Expand 10 after
225 } 233 }
226 void _push(const VarList &Sources) { 234 void _push(const VarList &Sources) {
227 Context.insert(InstARM32Push::create(Func, Sources)); 235 Context.insert(InstARM32Push::create(Func, Sources));
228 } 236 }
229 void _pop(const VarList &Dests) { 237 void _pop(const VarList &Dests) {
230 Context.insert(InstARM32Pop::create(Func, Dests)); 238 Context.insert(InstARM32Pop::create(Func, Dests));
231 // Mark dests as modified. 239 // Mark dests as modified.
232 for (Variable *Dest : Dests) 240 for (Variable *Dest : Dests)
233 Context.insert(InstFakeDef::create(Func, Dest)); 241 Context.insert(InstFakeDef::create(Func, Dest));
234 } 242 }
243 void _rsb(Variable *Dest, Variable *Src0, Operand *Src1,
244 CondARM32::Cond Pred = CondARM32::AL) {
245 Context.insert(InstARM32Rsb::create(Func, Dest, Src0, Src1, Pred));
246 }
235 void _sbc(Variable *Dest, Variable *Src0, Operand *Src1, 247 void _sbc(Variable *Dest, Variable *Src0, Operand *Src1,
236 CondARM32::Cond Pred = CondARM32::AL) { 248 CondARM32::Cond Pred = CondARM32::AL) {
237 Context.insert(InstARM32Sbc::create(Func, Dest, Src0, Src1, Pred)); 249 Context.insert(InstARM32Sbc::create(Func, Dest, Src0, Src1, Pred));
238 } 250 }
239 void _sbcs(Variable *Dest, Variable *Src0, Operand *Src1, 251 void _sbcs(Variable *Dest, Variable *Src0, Operand *Src1,
240 CondARM32::Cond Pred = CondARM32::AL) { 252 CondARM32::Cond Pred = CondARM32::AL) {
241 const bool SetFlags = true; 253 const bool SetFlags = true;
242 Context.insert( 254 Context.insert(
243 InstARM32Sbc::create(Func, Dest, Src0, Src1, Pred, SetFlags)); 255 InstARM32Sbc::create(Func, Dest, Src0, Src1, Pred, SetFlags));
244 } 256 }
245 void _str(Variable *Value, OperandARM32Mem *Addr, 257 void _str(Variable *Value, OperandARM32Mem *Addr,
246 CondARM32::Cond Pred = CondARM32::AL) { 258 CondARM32::Cond Pred = CondARM32::AL) {
247 Context.insert(InstARM32Str::create(Func, Value, Addr, Pred)); 259 Context.insert(InstARM32Str::create(Func, Value, Addr, Pred));
248 } 260 }
249 void _sub(Variable *Dest, Variable *Src0, Operand *Src1, 261 void _sub(Variable *Dest, Variable *Src0, Operand *Src1,
250 CondARM32::Cond Pred = CondARM32::AL) { 262 CondARM32::Cond Pred = CondARM32::AL) {
251 Context.insert(InstARM32Sub::create(Func, Dest, Src0, Src1, Pred)); 263 Context.insert(InstARM32Sub::create(Func, Dest, Src0, Src1, Pred));
252 } 264 }
253 void _subs(Variable *Dest, Variable *Src0, Operand *Src1, 265 void _subs(Variable *Dest, Variable *Src0, Operand *Src1,
254 CondARM32::Cond Pred = CondARM32::AL) { 266 CondARM32::Cond Pred = CondARM32::AL) {
255 const bool SetFlags = true; 267 const bool SetFlags = true;
256 Context.insert( 268 Context.insert(
257 InstARM32Sub::create(Func, Dest, Src0, Src1, Pred, SetFlags)); 269 InstARM32Sub::create(Func, Dest, Src0, Src1, Pred, SetFlags));
258 } 270 }
271 void _sxt(Variable *Dest, Variable *Src0,
272 CondARM32::Cond Pred = CondARM32::AL) {
273 Context.insert(InstARM32Sxt::create(Func, Dest, Src0, Pred));
274 }
259 void _ret(Variable *LR, Variable *Src0 = nullptr) { 275 void _ret(Variable *LR, Variable *Src0 = nullptr) {
260 Context.insert(InstARM32Ret::create(Func, LR, Src0)); 276 Context.insert(InstARM32Ret::create(Func, LR, Src0));
261 } 277 }
262 void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0, 278 void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0,
263 Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) { 279 Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) {
264 Context.insert( 280 Context.insert(
265 InstARM32Umull::create(Func, DestLo, DestHi, Src0, Src1, Pred)); 281 InstARM32Umull::create(Func, DestLo, DestHi, Src0, Src1, Pred));
266 // Model the modification to the second dest as a fake def. 282 // Model the modification to the second dest as a fake def.
267 // Note that the def is not predicated. 283 // Note that the def is not predicated.
268 Context.insert(InstFakeDef::create(Func, DestHi, DestLo)); 284 Context.insert(InstFakeDef::create(Func, DestHi, DestLo));
269 } 285 }
286 void _uxt(Variable *Dest, Variable *Src0,
287 CondARM32::Cond Pred = CondARM32::AL) {
288 Context.insert(InstARM32Uxt::create(Func, Dest, Src0, Pred));
289 }
270 290
271 bool UsesFramePointer; 291 bool UsesFramePointer;
272 bool NeedsStackAlignment; 292 bool NeedsStackAlignment;
273 bool MaybeLeafFunc; 293 bool MaybeLeafFunc;
274 size_t SpillAreaSizeBytes; 294 size_t SpillAreaSizeBytes;
275 llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; 295 llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
276 llvm::SmallBitVector ScratchRegs; 296 llvm::SmallBitVector ScratchRegs;
277 llvm::SmallBitVector RegsUsed; 297 llvm::SmallBitVector RegsUsed;
278 VarList PhysicalRegisters[IceType_NUM]; 298 VarList PhysicalRegisters[IceType_NUM];
279 static IceString RegNames[]; 299 static IceString RegNames[];
(...skipping 20 matching lines...) Expand all
300 320
301 private: 321 private:
302 void lowerGlobal(const VariableDeclaration &Var) const; 322 void lowerGlobal(const VariableDeclaration &Var) const;
303 ~TargetDataARM32() override {} 323 ~TargetDataARM32() override {}
304 template <typename T> static void emitConstantPool(GlobalContext *Ctx); 324 template <typename T> static void emitConstantPool(GlobalContext *Ctx);
305 }; 325 };
306 326
307 } // end of namespace Ice 327 } // end of namespace Ice
308 328
309 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H 329 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H
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