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1 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===// | 1 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file declares the InstARM32 and OperandARM32 classes and | 10 // This file declares the InstARM32 and OperandARM32 classes and |
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252 InstARM32() = delete; | 252 InstARM32() = delete; |
253 InstARM32(const InstARM32 &) = delete; | 253 InstARM32(const InstARM32 &) = delete; |
254 InstARM32 &operator=(const InstARM32 &) = delete; | 254 InstARM32 &operator=(const InstARM32 &) = delete; |
255 | 255 |
256 public: | 256 public: |
257 enum InstKindARM32 { | 257 enum InstKindARM32 { |
258 k__Start = Inst::Target, | 258 k__Start = Inst::Target, |
259 Adc, | 259 Adc, |
260 Add, | 260 Add, |
261 And, | 261 And, |
| 262 Asr, |
262 Bic, | 263 Bic, |
263 Br, | 264 Br, |
264 Call, | 265 Call, |
265 Cmp, | 266 Cmp, |
266 Eor, | 267 Eor, |
267 Ldr, | 268 Ldr, |
268 Lsl, | 269 Lsl, |
| 270 Lsr, |
269 Mla, | 271 Mla, |
270 Mov, | 272 Mov, |
271 Movt, | 273 Movt, |
272 Movw, | 274 Movw, |
273 Mul, | 275 Mul, |
274 Mvn, | 276 Mvn, |
275 Orr, | 277 Orr, |
276 Pop, | 278 Pop, |
277 Push, | 279 Push, |
278 Ret, | 280 Ret, |
| 281 Rsb, |
279 Sbc, | 282 Sbc, |
280 Str, | 283 Str, |
281 Sub, | 284 Sub, |
282 Umull | 285 Sxt, |
| 286 Umull, |
| 287 Uxt |
283 }; | 288 }; |
284 | 289 |
285 static const char *getWidthString(Type Ty); | 290 static const char *getWidthString(Type Ty); |
286 static CondARM32::Cond getOppositeCondition(CondARM32::Cond Cond); | 291 static CondARM32::Cond getOppositeCondition(CondARM32::Cond Cond); |
287 | 292 |
288 void dump(const Cfg *Func) const override; | 293 void dump(const Cfg *Func) const override; |
289 | 294 |
290 protected: | 295 protected: |
291 InstARM32(Cfg *Func, InstKindARM32 Kind, SizeT Maxsrcs, Variable *Dest) | 296 InstARM32(Cfg *Func, InstKindARM32 Kind, SizeT Maxsrcs, Variable *Dest) |
292 : InstTarget(Func, static_cast<InstKind>(Kind), Maxsrcs, Dest) {} | 297 : InstTarget(Func, static_cast<InstKind>(Kind), Maxsrcs, Dest) {} |
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307 CondARM32::Cond Predicate) | 312 CondARM32::Cond Predicate) |
308 : InstARM32(Func, Kind, Maxsrcs, Dest), Predicate(Predicate) {} | 313 : InstARM32(Func, Kind, Maxsrcs, Dest), Predicate(Predicate) {} |
309 | 314 |
310 CondARM32::Cond getPredicate() const { return Predicate; } | 315 CondARM32::Cond getPredicate() const { return Predicate; } |
311 void setPredicate(CondARM32::Cond Pred) { Predicate = Pred; } | 316 void setPredicate(CondARM32::Cond Pred) { Predicate = Pred; } |
312 | 317 |
313 static const char *predString(CondARM32::Cond Predicate); | 318 static const char *predString(CondARM32::Cond Predicate); |
314 void dumpOpcodePred(Ostream &Str, const char *Opcode, Type Ty) const; | 319 void dumpOpcodePred(Ostream &Str, const char *Opcode, Type Ty) const; |
315 | 320 |
316 // Shared emit routines for common forms of instructions. | 321 // Shared emit routines for common forms of instructions. |
| 322 static void emitUnaryopGPR(const char *Opcode, const InstARM32Pred *Inst, |
| 323 const Cfg *Func); |
317 static void emitTwoAddr(const char *Opcode, const InstARM32Pred *Inst, | 324 static void emitTwoAddr(const char *Opcode, const InstARM32Pred *Inst, |
318 const Cfg *Func); | 325 const Cfg *Func); |
319 static void emitThreeAddr(const char *Opcode, const InstARM32Pred *Inst, | 326 static void emitThreeAddr(const char *Opcode, const InstARM32Pred *Inst, |
320 const Cfg *Func, bool SetFlags); | 327 const Cfg *Func, bool SetFlags); |
321 | 328 |
322 protected: | 329 protected: |
323 CondARM32::Cond Predicate; | 330 CondARM32::Cond Predicate; |
324 }; | 331 }; |
325 | 332 |
326 template <typename StreamType> | 333 template <typename StreamType> |
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338 | 345 |
339 public: | 346 public: |
340 static InstARM32UnaryopGPR *create(Cfg *Func, Variable *Dest, Operand *Src, | 347 static InstARM32UnaryopGPR *create(Cfg *Func, Variable *Dest, Operand *Src, |
341 CondARM32::Cond Predicate) { | 348 CondARM32::Cond Predicate) { |
342 return new (Func->allocate<InstARM32UnaryopGPR>()) | 349 return new (Func->allocate<InstARM32UnaryopGPR>()) |
343 InstARM32UnaryopGPR(Func, Dest, Src, Predicate); | 350 InstARM32UnaryopGPR(Func, Dest, Src, Predicate); |
344 } | 351 } |
345 void emit(const Cfg *Func) const override { | 352 void emit(const Cfg *Func) const override { |
346 if (!ALLOW_DUMP) | 353 if (!ALLOW_DUMP) |
347 return; | 354 return; |
348 Ostream &Str = Func->getContext()->getStrEmit(); | 355 emitUnaryopGPR(Opcode, this, Func); |
349 assert(getSrcSize() == 1); | |
350 Str << "\t" << Opcode << "\t"; | |
351 getDest()->emit(Func); | |
352 Str << ", "; | |
353 getSrc(0)->emit(Func); | |
354 } | 356 } |
355 void emitIAS(const Cfg *Func) const override { | 357 void emitIAS(const Cfg *Func) const override { |
356 (void)Func; | 358 (void)Func; |
357 llvm_unreachable("Not yet implemented"); | 359 llvm_unreachable("Not yet implemented"); |
358 } | 360 } |
359 void dump(const Cfg *Func) const override { | 361 void dump(const Cfg *Func) const override { |
360 if (!ALLOW_DUMP) | 362 if (!ALLOW_DUMP) |
361 return; | 363 return; |
362 Ostream &Str = Func->getContext()->getStrDump(); | 364 Ostream &Str = Func->getContext()->getStrDump(); |
363 dumpDest(Func); | 365 dumpDest(Func); |
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514 addSource(Src2); | 516 addSource(Src2); |
515 } | 517 } |
516 ~InstARM32ThreeAddrGPR() override {} | 518 ~InstARM32ThreeAddrGPR() override {} |
517 static const char *Opcode; | 519 static const char *Opcode; |
518 bool SetFlags; | 520 bool SetFlags; |
519 }; | 521 }; |
520 | 522 |
521 typedef InstARM32ThreeAddrGPR<InstARM32::Adc> InstARM32Adc; | 523 typedef InstARM32ThreeAddrGPR<InstARM32::Adc> InstARM32Adc; |
522 typedef InstARM32ThreeAddrGPR<InstARM32::Add> InstARM32Add; | 524 typedef InstARM32ThreeAddrGPR<InstARM32::Add> InstARM32Add; |
523 typedef InstARM32ThreeAddrGPR<InstARM32::And> InstARM32And; | 525 typedef InstARM32ThreeAddrGPR<InstARM32::And> InstARM32And; |
| 526 typedef InstARM32ThreeAddrGPR<InstARM32::Asr> InstARM32Asr; |
524 typedef InstARM32ThreeAddrGPR<InstARM32::Bic> InstARM32Bic; | 527 typedef InstARM32ThreeAddrGPR<InstARM32::Bic> InstARM32Bic; |
525 typedef InstARM32ThreeAddrGPR<InstARM32::Eor> InstARM32Eor; | 528 typedef InstARM32ThreeAddrGPR<InstARM32::Eor> InstARM32Eor; |
526 typedef InstARM32ThreeAddrGPR<InstARM32::Lsl> InstARM32Lsl; | 529 typedef InstARM32ThreeAddrGPR<InstARM32::Lsl> InstARM32Lsl; |
| 530 typedef InstARM32ThreeAddrGPR<InstARM32::Lsr> InstARM32Lsr; |
527 typedef InstARM32ThreeAddrGPR<InstARM32::Mul> InstARM32Mul; | 531 typedef InstARM32ThreeAddrGPR<InstARM32::Mul> InstARM32Mul; |
528 typedef InstARM32ThreeAddrGPR<InstARM32::Orr> InstARM32Orr; | 532 typedef InstARM32ThreeAddrGPR<InstARM32::Orr> InstARM32Orr; |
| 533 typedef InstARM32ThreeAddrGPR<InstARM32::Rsb> InstARM32Rsb; |
529 typedef InstARM32ThreeAddrGPR<InstARM32::Sbc> InstARM32Sbc; | 534 typedef InstARM32ThreeAddrGPR<InstARM32::Sbc> InstARM32Sbc; |
530 typedef InstARM32ThreeAddrGPR<InstARM32::Sub> InstARM32Sub; | 535 typedef InstARM32ThreeAddrGPR<InstARM32::Sub> InstARM32Sub; |
531 // Move instruction (variable <- flex). This is more of a pseudo-inst. | 536 // Move instruction (variable <- flex). This is more of a pseudo-inst. |
532 // If var is a register, then we use "mov". If var is stack, then we use | 537 // If var is a register, then we use "mov". If var is stack, then we use |
533 // "str" to store to the stack. | 538 // "str" to store to the stack. |
534 typedef InstARM32Movlike<InstARM32::Mov> InstARM32Mov; | 539 typedef InstARM32Movlike<InstARM32::Mov> InstARM32Mov; |
535 // MovT leaves the bottom bits alone so dest is also a source. | 540 // MovT leaves the bottom bits alone so dest is also a source. |
536 // This helps indicate that a previous MovW setting dest is not dead code. | 541 // This helps indicate that a previous MovW setting dest is not dead code. |
537 typedef InstARM32TwoAddrGPR<InstARM32::Movt> InstARM32Movt; | 542 typedef InstARM32TwoAddrGPR<InstARM32::Movt> InstARM32Movt; |
538 typedef InstARM32UnaryopGPR<InstARM32::Movw> InstARM32Movw; | 543 typedef InstARM32UnaryopGPR<InstARM32::Movw> InstARM32Movw; |
539 typedef InstARM32UnaryopGPR<InstARM32::Mvn> InstARM32Mvn; | 544 typedef InstARM32UnaryopGPR<InstARM32::Mvn> InstARM32Mvn; |
| 545 // Technically, the uxt{b,h} and sxt{b,h} instructions have a rotation |
| 546 // operand as well (rotate source by 8, 16, 24 bits prior to extending), |
| 547 // but we aren't using that for now, so just model as a Unaryop. |
| 548 typedef InstARM32UnaryopGPR<InstARM32::Sxt> InstARM32Sxt; |
| 549 typedef InstARM32UnaryopGPR<InstARM32::Uxt> InstARM32Uxt; |
540 | 550 |
541 // Direct branch instruction. | 551 // Direct branch instruction. |
542 class InstARM32Br : public InstARM32Pred { | 552 class InstARM32Br : public InstARM32Pred { |
543 InstARM32Br() = delete; | 553 InstARM32Br() = delete; |
544 InstARM32Br(const InstARM32Br &) = delete; | 554 InstARM32Br(const InstARM32Br &) = delete; |
545 InstARM32Br &operator=(const InstARM32Br &) = delete; | 555 InstARM32Br &operator=(const InstARM32Br &) = delete; |
546 | 556 |
547 public: | 557 public: |
548 // Create a conditional branch to one of two nodes. | 558 // Create a conditional branch to one of two nodes. |
549 static InstARM32Br *create(Cfg *Func, CfgNode *TargetTrue, | 559 static InstARM32Br *create(Cfg *Func, CfgNode *TargetTrue, |
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818 // Declare partial template specializations of emit() methods that | 828 // Declare partial template specializations of emit() methods that |
819 // already have default implementations. Without this, there is the | 829 // already have default implementations. Without this, there is the |
820 // possibility of ODR violations and link errors. | 830 // possibility of ODR violations and link errors. |
821 | 831 |
822 template <> void InstARM32Movw::emit(const Cfg *Func) const; | 832 template <> void InstARM32Movw::emit(const Cfg *Func) const; |
823 template <> void InstARM32Movt::emit(const Cfg *Func) const; | 833 template <> void InstARM32Movt::emit(const Cfg *Func) const; |
824 | 834 |
825 } // end of namespace Ice | 835 } // end of namespace Ice |
826 | 836 |
827 #endif // SUBZERO_SRC_ICEINSTARM32_H | 837 #endif // SUBZERO_SRC_ICEINSTARM32_H |
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