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1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// | 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file implements the InstARM32 and OperandARM32 classes, | 10 // This file implements the InstARM32 and OperandARM32 classes, |
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70 | 70 |
71 void InstARM32Pred::dumpOpcodePred(Ostream &Str, const char *Opcode, | 71 void InstARM32Pred::dumpOpcodePred(Ostream &Str, const char *Opcode, |
72 Type Ty) const { | 72 Type Ty) const { |
73 Str << Opcode << getPredicate() << "." << Ty; | 73 Str << Opcode << getPredicate() << "." << Ty; |
74 } | 74 } |
75 | 75 |
76 CondARM32::Cond InstARM32::getOppositeCondition(CondARM32::Cond Cond) { | 76 CondARM32::Cond InstARM32::getOppositeCondition(CondARM32::Cond Cond) { |
77 return InstARM32CondAttributes[Cond].Opposite; | 77 return InstARM32CondAttributes[Cond].Opposite; |
78 } | 78 } |
79 | 79 |
| 80 void InstARM32Pred::emitUnaryopGPR(const char *Opcode, |
| 81 const InstARM32Pred *Inst, const Cfg *Func) { |
| 82 Ostream &Str = Func->getContext()->getStrEmit(); |
| 83 assert(Inst->getSrcSize() == 1); |
| 84 Type SrcTy = Inst->getSrc(0)->getType(); |
| 85 Type DestTy = Inst->getDest()->getType(); |
| 86 Str << "\t" << Opcode; |
| 87 // Sxt and Uxt need source type width letter to define the operation. |
| 88 // The other unary operations have the same source and dest type and |
| 89 // as a result need only one letter. |
| 90 if (SrcTy != DestTy) |
| 91 Str << getWidthString(SrcTy); |
| 92 Str << "\t"; |
| 93 Inst->getDest()->emit(Func); |
| 94 Str << ", "; |
| 95 Inst->getSrc(0)->emit(Func); |
| 96 } |
| 97 |
80 void InstARM32Pred::emitTwoAddr(const char *Opcode, const InstARM32Pred *Inst, | 98 void InstARM32Pred::emitTwoAddr(const char *Opcode, const InstARM32Pred *Inst, |
81 const Cfg *Func) { | 99 const Cfg *Func) { |
82 if (!ALLOW_DUMP) | 100 if (!ALLOW_DUMP) |
83 return; | 101 return; |
84 Ostream &Str = Func->getContext()->getStrEmit(); | 102 Ostream &Str = Func->getContext()->getStrEmit(); |
85 assert(Inst->getSrcSize() == 2); | 103 assert(Inst->getSrcSize() == 2); |
86 Variable *Dest = Inst->getDest(); | 104 Variable *Dest = Inst->getDest(); |
87 assert(Dest == Inst->getSrc(0)); | 105 assert(Dest == Inst->getSrc(0)); |
88 Str << "\t" << Opcode << Inst->getPredicate() << "\t"; | 106 Str << "\t" << Opcode << Inst->getPredicate() << "\t"; |
89 Dest->emit(Func); | 107 Dest->emit(Func); |
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298 addSource(Src1); | 316 addSource(Src1); |
299 } | 317 } |
300 | 318 |
301 // ======================== Dump routines ======================== // | 319 // ======================== Dump routines ======================== // |
302 | 320 |
303 // Two-addr ops | 321 // Two-addr ops |
304 template <> const char *InstARM32Movt::Opcode = "movt"; | 322 template <> const char *InstARM32Movt::Opcode = "movt"; |
305 // Unary ops | 323 // Unary ops |
306 template <> const char *InstARM32Movw::Opcode = "movw"; | 324 template <> const char *InstARM32Movw::Opcode = "movw"; |
307 template <> const char *InstARM32Mvn::Opcode = "mvn"; | 325 template <> const char *InstARM32Mvn::Opcode = "mvn"; |
| 326 template <> const char *InstARM32Sxt::Opcode = "sxt"; // still requires b/h |
| 327 template <> const char *InstARM32Uxt::Opcode = "uxt"; // still requires b/h |
308 // Mov-like ops | 328 // Mov-like ops |
309 template <> const char *InstARM32Mov::Opcode = "mov"; | 329 template <> const char *InstARM32Mov::Opcode = "mov"; |
310 // Three-addr ops | 330 // Three-addr ops |
311 template <> const char *InstARM32Adc::Opcode = "adc"; | 331 template <> const char *InstARM32Adc::Opcode = "adc"; |
312 template <> const char *InstARM32Add::Opcode = "add"; | 332 template <> const char *InstARM32Add::Opcode = "add"; |
313 template <> const char *InstARM32And::Opcode = "and"; | 333 template <> const char *InstARM32And::Opcode = "and"; |
| 334 template <> const char *InstARM32Asr::Opcode = "asr"; |
314 template <> const char *InstARM32Bic::Opcode = "bic"; | 335 template <> const char *InstARM32Bic::Opcode = "bic"; |
315 template <> const char *InstARM32Eor::Opcode = "eor"; | 336 template <> const char *InstARM32Eor::Opcode = "eor"; |
316 template <> const char *InstARM32Lsl::Opcode = "lsl"; | 337 template <> const char *InstARM32Lsl::Opcode = "lsl"; |
| 338 template <> const char *InstARM32Lsr::Opcode = "lsr"; |
317 template <> const char *InstARM32Mul::Opcode = "mul"; | 339 template <> const char *InstARM32Mul::Opcode = "mul"; |
318 template <> const char *InstARM32Orr::Opcode = "orr"; | 340 template <> const char *InstARM32Orr::Opcode = "orr"; |
| 341 template <> const char *InstARM32Rsb::Opcode = "rsb"; |
319 template <> const char *InstARM32Sbc::Opcode = "sbc"; | 342 template <> const char *InstARM32Sbc::Opcode = "sbc"; |
320 template <> const char *InstARM32Sub::Opcode = "sub"; | 343 template <> const char *InstARM32Sub::Opcode = "sub"; |
321 | 344 |
322 void InstARM32::dump(const Cfg *Func) const { | 345 void InstARM32::dump(const Cfg *Func) const { |
323 if (!ALLOW_DUMP) | 346 if (!ALLOW_DUMP) |
324 return; | 347 return; |
325 Ostream &Str = Func->getContext()->getStrDump(); | 348 Ostream &Str = Func->getContext()->getStrDump(); |
326 Str << "[ARM32] "; | 349 Str << "[ARM32] "; |
327 Inst::dump(Func); | 350 Inst::dump(Func); |
328 } | 351 } |
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678 void InstARM32Str::emitIAS(const Cfg *Func) const { | 701 void InstARM32Str::emitIAS(const Cfg *Func) const { |
679 assert(getSrcSize() == 2); | 702 assert(getSrcSize() == 2); |
680 (void)Func; | 703 (void)Func; |
681 llvm_unreachable("Not yet implemented"); | 704 llvm_unreachable("Not yet implemented"); |
682 } | 705 } |
683 | 706 |
684 void InstARM32Str::dump(const Cfg *Func) const { | 707 void InstARM32Str::dump(const Cfg *Func) const { |
685 if (!ALLOW_DUMP) | 708 if (!ALLOW_DUMP) |
686 return; | 709 return; |
687 Ostream &Str = Func->getContext()->getStrDump(); | 710 Ostream &Str = Func->getContext()->getStrDump(); |
688 dumpOpcodePred(Str, "str", getDest()->getType()); | 711 Type Ty = getSrc(0)->getType(); |
| 712 dumpOpcodePred(Str, "str", Ty); |
689 Str << " "; | 713 Str << " "; |
690 getSrc(1)->dump(Func); | 714 getSrc(1)->dump(Func); |
691 Str << ", "; | 715 Str << ", "; |
692 getSrc(0)->dump(Func); | 716 getSrc(0)->dump(Func); |
693 } | 717 } |
694 | 718 |
695 void InstARM32Umull::emit(const Cfg *Func) const { | 719 void InstARM32Umull::emit(const Cfg *Func) const { |
696 if (!ALLOW_DUMP) | 720 if (!ALLOW_DUMP) |
697 return; | 721 return; |
698 Ostream &Str = Func->getContext()->getStrEmit(); | 722 Ostream &Str = Func->getContext()->getStrEmit(); |
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835 if (getShiftOp() != kNoShift) { | 859 if (getShiftOp() != kNoShift) { |
836 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " "; | 860 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " "; |
837 if (Func) | 861 if (Func) |
838 getShiftAmt()->dump(Func); | 862 getShiftAmt()->dump(Func); |
839 else | 863 else |
840 getShiftAmt()->dump(Str); | 864 getShiftAmt()->dump(Str); |
841 } | 865 } |
842 } | 866 } |
843 | 867 |
844 } // end of namespace Ice | 868 } // end of namespace Ice |
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