Subzero ARM32: Lower shift and zext, sext, and trunc.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstARM32 and OperandARM32 classes,
@@ skipping 59 matching lines @@
 
 void InstARM32Pred::dumpOpcodePred(Ostream &Str, const char *Opcode,
                                    Type Ty) const {
   Str << Opcode << getPredicate() << "." << Ty;
 }
 
 CondARM32::Cond InstARM32::getOppositeCondition(CondARM32::Cond Cond) {
   return InstARM32CondAttributes[Cond].Opposite;
 }
 
+void InstARM32Pred::emitUnaryopGPR(const char *Opcode,
+                                   const InstARM32Pred *Inst, const Cfg *Func) {
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(Inst->getSrcSize() == 1);
+  Type SrcTy = Inst->getSrc(0)->getType();
+  Type DestTy = Inst->getDest()->getType();
+  Str << "\t" << Opcode;
+  // Sxt and Uxt need source type width letter to define the operation.
+  // The other unary operations have the same source and dest type and
+  // as a result need only one letter.
+  if (SrcTy != DestTy)
+    Str << getWidthString(SrcTy);
+  Str << "\t";
+  Inst->getDest()->emit(Func);
+  Str << ", ";
+  Inst->getSrc(0)->emit(Func);
+}
+
 void InstARM32Pred::emitTwoAddr(const char *Opcode, const InstARM32Pred *Inst,
                                 const Cfg *Func) {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 2);
   Variable *Dest = Inst->getDest();
   assert(Dest == Inst->getSrc(0));
   Str << "\t" << Opcode << Inst->getPredicate() << "\t";
   Dest->emit(Func);
@@ skipping 208 matching lines @@
   addSource(Src1);
 }
 
 // ======================== Dump routines ======================== //
 
 // Two-addr ops
 template <> const char *InstARM32Movt::Opcode = "movt";
 // Unary ops
 template <> const char *InstARM32Movw::Opcode = "movw";
 template <> const char *InstARM32Mvn::Opcode = "mvn";
+template <> const char *InstARM32Sxt::Opcode = "sxt"; // still requires b/h
+template <> const char *InstARM32Uxt::Opcode = "uxt"; // still requires b/h
 // Mov-like ops
 template <> const char *InstARM32Mov::Opcode = "mov";
 // Three-addr ops
 template <> const char *InstARM32Adc::Opcode = "adc";
 template <> const char *InstARM32Add::Opcode = "add";
 template <> const char *InstARM32And::Opcode = "and";
+template <> const char *InstARM32Asr::Opcode = "asr";
 template <> const char *InstARM32Bic::Opcode = "bic";
 template <> const char *InstARM32Eor::Opcode = "eor";
 template <> const char *InstARM32Lsl::Opcode = "lsl";
+template <> const char *InstARM32Lsr::Opcode = "lsr";
 template <> const char *InstARM32Mul::Opcode = "mul";
 template <> const char *InstARM32Orr::Opcode = "orr";
+template <> const char *InstARM32Rsb::Opcode = "rsb";
 template <> const char *InstARM32Sbc::Opcode = "sbc";
 template <> const char *InstARM32Sub::Opcode = "sub";
 
 void InstARM32::dump(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "[ARM32] ";
   Inst::dump(Func);
 }
@@ skipping 349 matching lines @@
 void InstARM32Str::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   (void)Func;
   llvm_unreachable("Not yet implemented");
 }
 
 void InstARM32Str::dump(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrDump();
-  dumpOpcodePred(Str, "str", getDest()->getType());
+  Type Ty = getSrc(0)->getType();
+  dumpOpcodePred(Str, "str", Ty);
   Str << " ";
   getSrc(1)->dump(Func);
   Str << ", ";
   getSrc(0)->dump(Func);
 }
 
 void InstARM32Umull::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
@@ skipping 136 matching lines @@
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     if (Func)
       getShiftAmt()->dump(Func);
     else
       getShiftAmt()->dump(Str);
   }
 }
 
 } // end of namespace Ice