Heuristically predict interference on the back edge and use it to minimize number of register reshu…

runtime/vm/flow_graph_allocator.cc

 // Copyright (c) 2012, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/flow_graph_allocator.h"
 
 #include "vm/bit_vector.h"
 #include "vm/intermediate_language.h"
 #include "vm/il_printer.h"
 #include "vm/flow_graph.h"
@@ skipping 44 matching lines @@
 }
 
 
 static intptr_t ToInstructionEnd(intptr_t pos) {
   return (pos | 1);
 }
 
 
 FlowGraphAllocator::FlowGraphAllocator(const FlowGraph& flow_graph)
   : flow_graph_(flow_graph),
+    reaching_defs_(flow_graph),
     mint_values_(NULL),
     block_order_(flow_graph.reverse_postorder()),
     postorder_(flow_graph.postorder()),
     live_out_(block_order_.length()),
     kill_(block_order_.length()),
     live_in_(block_order_.length()),
     vreg_count_(flow_graph.max_virtual_register_number()),
     live_ranges_(flow_graph.max_virtual_register_number()),
     cpu_regs_(),
     xmm_regs_(),
@@ skipping 64 matching lines @@
       Instruction* current = it.Current();
 
       // Handle definitions.
       Definition* current_def = current->AsDefinition();
       if ((current_def != NULL) && current_def->HasSSATemp()) {
         kill->Add(current_def->ssa_temp_index());
         live_in->Remove(current_def->ssa_temp_index());
       }
 
       // Handle uses.
+      LocationSummary* locs = current->locs();
+      ASSERT(locs->input_count() == current->InputCount());
       for (intptr_t j = 0; j < current->InputCount(); j++) {
         Value* input = current->InputAt(j);
         const intptr_t use = input->definition()->ssa_temp_index();
+
+        ASSERT(!locs->in(j).IsConstant() || input->BindsToConstant());
+        if (locs->in(j).IsConstant()) continue;
+
         live_in->Add(use);
       }
 
       // Add non-argument uses from the deoptimization environment (pushed
       // arguments are not allocated by the register allocator).
       if (current->env() != NULL) {
         for (Environment::DeepIterator env_it(current->env());
              !env_it.Done();
              env_it.Advance()) {
           Value* value = env_it.CurrentValue();
@@ skipping 13 matching lines @@
           PhiInstr* phi = (*join->phis())[j];
           if (phi == NULL) continue;
 
           kill->Add(phi->ssa_temp_index());
           live_in->Remove(phi->ssa_temp_index());
 
           // If phi-operand is not defined by a predecessor it must be marked
           // live-in for a predecessor.
           for (intptr_t k = 0; k < phi->InputCount(); k++) {
             Value* val = phi->InputAt(k);
+            if (val->BindsToConstant()) continue;
+
             BlockEntryInstr* pred = block->PredecessorAt(k);
             const intptr_t use = val->definition()->ssa_temp_index();
             if (!kill_[pred->postorder_number()]->Contains(use)) {
               live_in_[pred->postorder_number()]->Add(use);
             }
           }
         }
       }
     }
   }
@@ skipping 315 matching lines @@
     use = use->next();
   }
 
   return true;
 }
 
 
 void FlowGraphAllocator::BuildLiveRanges() {
   const intptr_t block_count = postorder_.length();
   ASSERT(postorder_.Last()->IsGraphEntry());
+  BitVector* current_interference_set = NULL;
   for (intptr_t i = 0; i < (block_count - 1); i++) {
     BlockEntryInstr* block = postorder_[i];
 
+    BlockInfo* block_info = BlockInfoAt(block->start_pos());
+
     // For every SSA value that is live out of this block, create an interval
     // that covers the whole block.  It will be shortened if we encounter a
     // definition of this value in this block.
     for (BitVector::Iterator it(live_out_[i]); !it.Done(); it.Advance()) {
       LiveRange* range = GetLiveRange(it.Current());
       range->AddUseInterval(block->start_pos(), block->end_pos());
     }
 
+    BlockInfo* loop_header = block_info->loop_header();
+    if ((loop_header != NULL) && (loop_header->last_block() == block)) {
+      current_interference_set =
+          new BitVector(flow_graph_.max_virtual_register_number());
+      ASSERT(loop_header->backedge_interference() == NULL);
+      loop_header->set_backedge_interference(
+          current_interference_set);
+    }
+
     // Connect outgoing phi-moves that were created in NumberInstructions
     // and find last instruction that contributes to liveness.
-    Instruction* current = ConnectOutgoingPhiMoves(block);
+    Instruction* current = ConnectOutgoingPhiMoves(block,
+                                                   current_interference_set);
 
     // Now process all instructions in reverse order.
     while (current != block) {
       // Skip parallel moves that we insert while processing instructions.
       if (!current->IsParallelMove()) {
-        ProcessOneInstruction(block, current);
+        ProcessOneInstruction(block, current, current_interference_set);
       }
       current = current->previous();
     }
 
 
     // Check if any values live into the loop can be spilled for free.
-    BlockInfo* block_info = BlockInfoAt(block->start_pos());
     if (block_info->is_loop_header()) {
+      current_interference_set = NULL;
       for (BitVector::Iterator it(live_in_[i]); !it.Done(); it.Advance()) {
         LiveRange* range = GetLiveRange(it.Current());
         if (HasOnlyUnconstrainedUsesInLoop(range, block_info)) {
           range->MarkHasOnlyUnconstrainedUsesInLoop(block_info->loop_id());
         }
       }
     }
 
     ConnectIncomingPhiMoves(block);
   }
@@ skipping 85 matching lines @@
 //
 //           i  i'
 //  value  --*--)
 //
 // can be read as: use interval for value starts somewhere before instruction
 // and extends until currently processed instruction, there is a use of value
 // at the start of the instruction.
 //
 
 Instruction* FlowGraphAllocator::ConnectOutgoingPhiMoves(
-    BlockEntryInstr* block) {
+    BlockEntryInstr* block, BitVector* interfere_at_backedge) {
   Instruction* last = block->last_instruction();
 
   GotoInstr* goto_instr = last->AsGoto();
   if (goto_instr == NULL) return last;
 
   // If we have a parallel move here then the successor block must be a
   // join with phis.  The phi inputs contribute uses to each predecessor
   // block (and the phi outputs contribute definitions in the successor
   // block).
   if (!goto_instr->HasParallelMove()) return goto_instr->previous();
@@ skipping 25 matching lines @@
       move_idx++;
       continue;
     }
 
     // Expected shape of live ranges:
     //
     //                 g  g'
     //      value    --*
     //
 
-    LiveRange* range = GetLiveRange(val->definition()->ssa_temp_index());
+    const intptr_t vreg = val->definition()->ssa_temp_index();
+    LiveRange* range = GetLiveRange(vreg);
+    if (interfere_at_backedge != NULL) interfere_at_backedge->Add(vreg);
 
     range->AddUseInterval(block->start_pos(), pos);
     range->AddHintedUse(pos, move->src_slot(), move->dest_slot());
 
     move->set_src(Location::PrefersRegister());
     move_idx++;
   }
 
   // Begin backward iteration with the instruction before the parallel
   // move.
@@ skipping 104 matching lines @@
 
     env->set_locations(locations);
     env = env->outer();
   }
 }
 
 
 // Create and update live ranges corresponding to instruction's inputs,
 // temporaries and output.
 void FlowGraphAllocator::ProcessOneInstruction(BlockEntryInstr* block,
-                                               Instruction* current) {
+                                               Instruction* current,
+                                               BitVector* interference_set) {
   LocationSummary* locs = current->locs();
 
   Definition* def = current->AsDefinition();
   if ((def != NULL) &&
       (def->AsConstant() != NULL) &&
       ((def->ssa_temp_index() == -1) ||
        (GetLiveRange(def->ssa_temp_index())->first_use() == NULL))) {
     // Drop definitions of constants that have no uses.
     locs->set_out(Location::NoLocation());
     return;
@@ skipping 223 matching lines @@
         GetLiveRange(input->ssa_temp_index());
     input_range->AddUseInterval(block->start_pos(), pos);
     input_range->AddUse(pos, move->src_slot());
 
     // Shorten output live range to the point of definition and add both input
     // and output uses slots to be filled by allocator.
     range->DefineAt(pos);
     range->AddHintedUse(pos, out, move->src_slot());
     range->AddUse(pos, move->dest_slot());
     range->AddUse(pos, locs->in_slot(0));
+
+    if ((interference_set != NULL) &&
+        (range->vreg() >= 0) &&
+        interference_set->Contains(range->vreg())) {
+      interference_set->Add(input->ssa_temp_index());
+    }
   } else {
     // Normal unallocated location that requires a register. Expected shape of
     // live range:
     //
     //                    i  i'
     //    output          [-------
     //
     ASSERT(locs->out().Equals(Location::RequiresRegister()) ||
            locs->out().Equals(Location::RequiresXmmRegister()));
 
@@ skipping 366 matching lines @@
     finger_.UpdateAfterSplit(first_use_after_split->pos());
   }
 
   return next_sibling_;
 }
 
 
 LiveRange* FlowGraphAllocator::SplitBetween(LiveRange* range,
                                             intptr_t from,
                                             intptr_t to) {
-  TRACE_ALLOC(OS::Print("split %"Pd" [%"Pd", %"Pd") between [%"Pd", %"Pd")\n",
+  TRACE_ALLOC(OS::Print("split v%"Pd" [%"Pd", %"Pd") between [%"Pd", %"Pd")\n",
                         range->vreg(), range->Start(), range->End(), from, to));
 
   intptr_t split_pos = kIllegalPosition;
 
   BlockInfo* split_block = BlockInfoAt(to);
   if (from < split_block->entry()->lifetime_position()) {
     // Interval [from, to) spans multiple blocks.
 
     // If last block is inside a loop prefer splitting at outermost loop's
     // header.
@@ skipping 17 matching lines @@
   ASSERT((split_pos != kIllegalPosition) && (from < split_pos));
 
   return range->SplitAt(split_pos);
 }
 
 
 void FlowGraphAllocator::SpillBetween(LiveRange* range,
                                       intptr_t from,
                                       intptr_t to) {
   ASSERT(from < to);
-  TRACE_ALLOC(OS::Print("spill %"Pd" [%"Pd", %"Pd") "
+  TRACE_ALLOC(OS::Print("spill v%"Pd" [%"Pd", %"Pd") "
                         "between [%"Pd", %"Pd")\n",
                         range->vreg(), range->Start(), range->End(), from, to));
   LiveRange* tail = range->SplitAt(from);
 
   if (tail->Start() < to) {
     // There is an intersection of tail and [from, to).
     LiveRange* tail_tail = SplitBetween(tail, tail->Start(), to);
     Spill(tail);
     AddToUnallocated(tail_tail);
   } else {
     // No intersection between tail and [from, to).
     AddToUnallocated(tail);
   }
 }
 
 
 void FlowGraphAllocator::SpillAfter(LiveRange* range, intptr_t from) {
-  TRACE_ALLOC(OS::Print("spill %"Pd" [%"Pd", %"Pd") after %"Pd"\n",
+  TRACE_ALLOC(OS::Print("spill v%"Pd" [%"Pd", %"Pd") after %"Pd"\n",
                         range->vreg(), range->Start(), range->End(), from));
 
   // When spilling the value inside the loop check if this spill can
   // be moved outside.
   BlockInfo* block_info = BlockInfoAt(from);
   if (block_info->is_loop_header() || (block_info->loop() != NULL)) {
     BlockInfo* loop_header =
         block_info->is_loop_header() ? block_info : block_info->loop();
 
     if ((range->Start() <= loop_header->entry()->start_pos()) &&
@@ skipping 86 matching lines @@
 
     const intptr_t pos = FirstIntersection(
         unallocated->finger()->first_pending_use_interval(),
         allocated_head);
     if (pos < intersection) intersection = pos;
   }
   return intersection;
 }
 
 
+void ReachingDefs::AddPhi(PhiInstr* phi) {
+  if (phi->reaching_defs() == NULL) {
+    phi->set_reaching_defs(
+        new BitVector(flow_graph_.max_virtual_register_number()));
+
+    // Compute initial set reaching defs set.
+    bool depends_on_phi = false;
+    for (intptr_t i = 0; i < phi->InputCount(); i++) {
+      Definition* input = phi->InputAt(i)->definition();
+      if (input->IsPhi()) {
+        depends_on_phi = true;
+      }
+      phi->reaching_defs()->Add(input->ssa_temp_index());
+    }
+
+    // If this phi depends on another phi then we need fix point iteration.
+    if (depends_on_phi) phis_.Add(phi);
+  }
+}
+
+
+void ReachingDefs::Compute() {
+  // Transitively collect all phis that are used by the given phi.
+  for (intptr_t i = 0; i < phis_.length(); i++) {
+    PhiInstr* phi = phis_[i];
+
+    // Add all phis that affect this phi to the list.
+    for (intptr_t i = 0; i < phi->InputCount(); i++) {
+      Definition* input = phi->InputAt(i)->definition();
+      if (input->IsPhi()) {
+        AddPhi(input->AsPhi());
+      }
+    }
+  }
+
+  // Propagate values until fix point is reached.
+  bool changed;
+  do {
+    changed = false;
+    for (intptr_t i = 0; i < phis_.length(); i++) {
+      PhiInstr* phi = phis_[i];
+      for (intptr_t i = 0; i < phi->InputCount(); i++) {
+        Definition* input = phi->InputAt(i)->definition();

[Florian Schneider, 2012/11/23 13:58:06]

Or shorter:

input_phi = phi->InputAt(i)->definition()->AsPhi();
if (input_phi != NULL) { ...

[Vyacheslav Egorov (Google), 2012/11/23 15:38:53]

Done.

+        if (input->IsPhi()) {
+          if (phi->reaching_defs()->AddAll(input->AsPhi()->reaching_defs())) {
+            changed = true;
+          }
+        }
+      }
+    }
+  } while (changed);
+
+  phis_.Clear();
+}
+
+
+BitVector* ReachingDefs::Get(PhiInstr* phi) {
+  if (phi->reaching_defs() == NULL) {
+    ASSERT(phis_.is_empty());
+    AddPhi(phi);
+    Compute();
+  }
+  return phi->reaching_defs();
+}
+
+
 bool FlowGraphAllocator::AllocateFreeRegister(LiveRange* unallocated) {
   intptr_t candidate = kNoRegister;
   intptr_t free_until = 0;
 
   // If hint is available try hint first.
   // TODO(vegorov): ensure that phis are hinted on the back edge.
   Location hint = unallocated->finger()->FirstHint();
   if (hint.IsMachineRegister()) {
     if (!blocked_registers_[hint.register_code()]) {
       free_until = FirstIntersectionWithAllocated(hint.register_code(),
                                                   unallocated);
       candidate = hint.register_code();
     }
 
-    TRACE_ALLOC(OS::Print("found hint "));
-    TRACE_ALLOC(hint.Print());
-    TRACE_ALLOC(OS::Print(" for %"Pd": free until %"Pd"\n",
-                          unallocated->vreg(), free_until));
+    TRACE_ALLOC(OS::Print("found hint %s for v%"Pd": free until %"Pd"\n",
+                          hint.Name(),
+                          unallocated->vreg(),
+                          free_until));
   } else if (free_until != kMaxPosition) {
     for (intptr_t reg = 0; reg < NumberOfRegisters(); ++reg) {
       if (!blocked_registers_[reg] && (registers_[reg].length() == 0)) {
         candidate = reg;
         free_until = kMaxPosition;
         break;
       }
     }
   }
 
+  // We have a very good candidate (either hinted to us or completely free).
+  // If we are in the loop try to reduce number of moves on the back edge by

[Florian Schneider, 2012/11/23 13:58:06]

Which loop? s/the/a/?

[Vyacheslav Egorov (Google), 2012/11/23 15:38:53]

Done.

+  // searching for a candidate that does not interfere with phis on the back
+  // edge.
+  BlockInfo* loop_header = BlockInfoAt(unallocated->Start())->loop_header();
+  if ((unallocated->vreg() >= 0) &&
+      (loop_header != NULL) &&
+      (free_until >= loop_header->last_block()->end_pos()) &&
+      loop_header->backedge_interference()->Contains(unallocated->vreg())) {
+    ASSERT(static_cast<intptr_t>(kNumberOfXmmRegisters) <=

[Florian Schneider, 2012/11/23 13:58:06]

COMPILE_ASSERT?

[Vyacheslav Egorov (Google), 2012/11/23 15:38:53]

COMPILE_ASSERT seems to be available only in debug.

+           kNumberOfCpuRegisters);
+    bool used_on_backedge[kNumberOfCpuRegisters] = { false };
+
+    for (PhiIterator it(loop_header->entry()->AsJoinEntry());
+         !it.Done();
+         it.Advance()) {
+      PhiInstr* phi = it.Current();
+      if (phi->is_alive()) {
+        const intptr_t phi_vreg = phi->ssa_temp_index();
+        LiveRange* range = GetLiveRange(phi_vreg);
+        if (range->assigned_location().kind() == register_kind_) {
+          const intptr_t reg = range->assigned_location().register_code();
+
+          if ((unallocated->vreg() >= 0) &&

[Florian Schneider, 2012/11/23 13:58:06]

This condition is already tested in line 1747.

[Vyacheslav Egorov (Google), 2012/11/23 15:38:53]

Done.

+              !reaching_defs_.Get(phi)->Contains(unallocated->vreg())) {
+            used_on_backedge[reg] = true;
+          }
+        }
+      }
+    }
+
+    if (used_on_backedge[candidate]) {
+      TRACE_ALLOC(OS::Print(
+          "considering %s for v%"Pd": has interference on the back edge"
+          " {loop [%"Pd", %"Pd")}\n",
+          MakeRegisterLocation(candidate, Location::kDouble).Name(),
+          unallocated->vreg(),
+          loop_header->entry()->start_pos(),
+          loop_header->last_block()->end_pos()));
+      for (intptr_t reg = 0; reg < NumberOfRegisters(); ++reg) {
+        if (blocked_registers_[reg] ||
+            (reg == candidate) ||
+            used_on_backedge[reg]) {
+          continue;
+        }
+
+        const intptr_t intersection =
+            FirstIntersectionWithAllocated(reg, unallocated);
+        if (intersection >= free_until) {
+          candidate = reg;
+          free_until = intersection;
+          TRACE_ALLOC(OS::Print(
+              "found %s for v%"Pd" with no interference on the back edge\n",
+              MakeRegisterLocation(candidate, Location::kDouble).Name(),
+              candidate));
+          break;
+        }
+      }
+    }
+  }
+
   ASSERT(0 <= kMaxPosition);
   if (free_until != kMaxPosition) {
     for (intptr_t reg = 0; reg < NumberOfRegisters(); ++reg) {
       if (blocked_registers_[reg] || (reg == candidate)) continue;
       const intptr_t intersection =
           FirstIntersectionWithAllocated(reg, unallocated);
       if (intersection > free_until) {
         candidate = reg;
         free_until = intersection;
         if (free_until == kMaxPosition) break;
       }
     }
   }
 
   // All registers are blocked by active ranges.
   if (free_until <= unallocated->Start()) return false;
 
   TRACE_ALLOC(OS::Print("assigning free register "));
   TRACE_ALLOC(MakeRegisterLocation(candidate, Location::kDouble).Print());
-  TRACE_ALLOC(OS::Print(" to %"Pd"\n", unallocated->vreg()));
+  TRACE_ALLOC(OS::Print(" to v%"Pd"\n", unallocated->vreg()));
 
   if (free_until != kMaxPosition) {
     // There was an intersection. Split unallocated.
     TRACE_ALLOC(OS::Print("  splitting at %"Pd"\n", free_until));
     LiveRange* tail = unallocated->SplitAt(free_until);
     AddToUnallocated(tail);
   }
 
   registers_[candidate].Add(unallocated);
   unallocated->set_assigned_location(
@@ skipping 82 matching lines @@
                              : unallocated->Start();
   if (free_until < register_use_pos) {
     // Can't acquire free register. Spill until we really need one.
     ASSERT(unallocated->Start() < ToInstructionStart(register_use_pos));
     SpillBetween(unallocated, unallocated->Start(), register_use->pos());
     return;
   }
 
   TRACE_ALLOC(OS::Print("assigning blocked register "));
   TRACE_ALLOC(MakeRegisterLocation(candidate, Location::kDouble).Print());
-  TRACE_ALLOC(OS::Print(" to live range %"Pd" until %"Pd"\n",
+  TRACE_ALLOC(OS::Print(" to live range v%"Pd" until %"Pd"\n",
                         unallocated->vreg(), blocked_at));
 
   if (blocked_at < unallocated->End()) {
     // Register is blocked before the end of the live range.  Split the range
     // at latest at blocked_at position.
     LiveRange* tail = SplitBetween(unallocated,
                                    unallocated->Start(),
                                    blocked_at + 1);
     AddToUnallocated(tail);
   }
@@ skipping 285 matching lines @@
 }
 #endif
 
 
 void FlowGraphAllocator::PrepareForAllocation(
   Location::Kind register_kind,
   intptr_t number_of_registers,
   const GrowableArray<LiveRange*>& unallocated,
   LiveRange** blocking_ranges,
   bool* blocked_registers) {
+  ASSERT(number_of_registers <= kNumberOfCpuRegisters);
   register_kind_ = register_kind;
   number_of_registers_ = number_of_registers;
 
   ASSERT(unallocated_.is_empty());
   unallocated_.AddArray(unallocated);
 
   for (intptr_t reg = 0; reg < number_of_registers; reg++) {
     blocked_registers_[reg] = blocked_registers[reg];
     ASSERT(registers_[reg].is_empty());
 
     LiveRange* range = blocking_ranges[reg];
     if (range != NULL) {
       range->finger()->Initialize(range);
       registers_[reg].Add(range);
     }
   }
 }
 
 
 void FlowGraphAllocator::AllocateUnallocatedRanges() {
 #if defined(DEBUG)
   ASSERT(UnallocatedIsSorted());
 #endif
 
   while (!unallocated_.is_empty()) {
     LiveRange* range = unallocated_.RemoveLast();
     const intptr_t start = range->Start();
-    TRACE_ALLOC(OS::Print("Processing live range for vreg %"Pd" "
+    TRACE_ALLOC(OS::Print("Processing live range for v%"Pd" "
                           "starting at %"Pd"\n",
                           range->vreg(),
                           start));
 
     // TODO(vegorov): eagerly spill liveranges without register uses.
     AdvanceActiveIntervals(start);
 
     if (!AllocateFreeRegister(range)) {
       AllocateAnyRegister(range);
     }
@@ skipping 16 matching lines @@
     ASSERT(GetLiveRange(range->vreg())->spill_slot().Equals(target));
     return true;
   }
   return false;
 }
 
 
 void FlowGraphAllocator::ConnectSplitSiblings(LiveRange* parent,
                                               BlockEntryInstr* source_block,
                                               BlockEntryInstr* target_block) {
-  TRACE_ALLOC(OS::Print("Connect source_block=%"Pd", target_block=%"Pd"\n",
+  TRACE_ALLOC(OS::Print("Connect v%"Pd" on the edge B%"Pd" -> B%"Pd"\n",
+                        parent->vreg(),
                         source_block->block_id(),
                         target_block->block_id()));
   if (parent->next_sibling() == NULL) {
     // Nothing to connect. The whole range was allocated to the same location.
-    TRACE_ALLOC(OS::Print("range %"Pd" has no siblings\n", parent->vreg()));
+    TRACE_ALLOC(OS::Print("range v%"Pd" has no siblings\n", parent->vreg()));
     return;
   }
 
   const intptr_t source_pos = source_block->end_pos() - 1;
   ASSERT(IsInstructionEndPosition(source_pos));
 
   const intptr_t target_pos = target_block->start_pos();
 
   Location target;
   Location source;
@@ skipping 16 matching lines @@
       ASSERT(target.IsInvalid());
       target = range->assigned_location();
 #if defined(DEBUG)
       target_cover = range;
 #endif
     }
 
     range = range->next_sibling();
   }
 
-  TRACE_ALLOC(OS::Print("connecting [%"Pd", %"Pd") [",
-                        source_cover->Start(), source_cover->End()));
-  TRACE_ALLOC(source.Print());
-  TRACE_ALLOC(OS::Print("] to [%"Pd", %"Pd") [",
-                        target_cover->Start(), target_cover->End()));
-  TRACE_ALLOC(target.Print());
-  TRACE_ALLOC(OS::Print("]\n"));
+  TRACE_ALLOC(OS::Print("connecting v%"Pd" between [%"Pd", %"Pd") {%s} "
+                        "to [%"Pd", %"Pd") {%s}\n",
+                        parent->vreg(),
+                        source_cover->Start(),
+                        source_cover->End(),
+                        source.Name(),
+                        target_cover->Start(),
+                        target_cover->End(),
+                        target.Name()));
 
   // Siblings were allocated to the same register.
   if (source.Equals(target)) return;
 
   // Values are eagerly spilled. Spill slot already contains appropriate value.
   if (TargetLocationIsSpillSlot(parent, target)) {
     return;
   }
 
   Instruction* last = source_block->last_instruction();
@@ skipping 152 matching lines @@
     OS::Print("-- [after ssa allocator] ir [%s] -------------\n",
               function.ToFullyQualifiedCString());
     FlowGraphPrinter printer(flow_graph_, true);
     printer.PrintBlocks();
     OS::Print("----------------------------------------------\n");
   }
 }
 
 
 }  // namespace dart