Add support for using MI bundles as bundle-locked groups on x86

lib/Target/X86/X86NaClRewritePass.cpp

 //=== X86NaClRewritePAss.cpp - Rewrite instructions for NaCl SFI --*- C++ -*-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains a pass that ensures stores and loads and stack/frame
@@ skipping 242 matching lines @@
     MI.getOperand(1).setReg(X86::RBP);
     MI.setDesc(TII->get(X86::MOV64rr));
     Opc = X86::MOV64rr;
   }
 
   // "MOV RBP, RSP" is already safe
   if (Opc == X86::MOV64rr && MI.getOperand(1).getReg() == X86::RBP) {
     return true;
   }
 
-  //  Promote 32-bit lea to 64-bit lea (does this ever happen?)
   assert(Opc != X86::LEA32r && "Invalid opcode in 64-bit mode!");
-  if (Opc == X86::LEA64_32r) {
+  if (Opc == X86::LEA64_32r){
+    unsigned BaseReg = MI.getOperand(1).getReg();
+    if (BaseReg != X86::EBP) {

[jvoung (off chromium), 2015/05/12 23:53:05]

Add a comment about why EBP is a special case?

Handled by NACL_SPADJ instead?

[Derek Schuff, 2015/05/13 00:44:50]

Done.

+      // Create a MachineInstr bundle (i.e. a bundle-locked group) and fix up
+      // the stack pointer by adding R15.  TODO(dschuff): generalize this for
+      // other uses if needed, and try to replace some pseudos if
+      // possible. Eventually replace with auto-sandboxing.
+      auto NextMBBI = MBBI;
+      ++NextMBBI;
+      BuildMI(MBB, NextMBBI, MBBI->getDebugLoc(),
+              TII->get(X86::ADD64rr), X86::RSP).addReg(X86::RSP).addReg(X86::R15);

[jvoung (off chromium), 2015/05/12 23:53:04]

80 col

[Derek Schuff, 2015/05/13 00:44:50]

Done.

+      MIBundleBuilder(MBB, MBBI, NextMBBI);
+      finalizeBundle(MBB, MBBI.getInstrIterator());
+      return true;
+    }
+
+    //  Promote 32-bit lea to 64-bit lea (does this ever happen?)
     unsigned DestReg = MI.getOperand(0).getReg();
-    unsigned BaseReg = MI.getOperand(1).getReg();
     unsigned Scale   = MI.getOperand(2).getImm();
     unsigned IndexReg = MI.getOperand(3).getReg();
     assert(DestReg == X86::ESP);
     assert(Scale == 1);
     assert(BaseReg == X86::EBP);
     assert(IndexReg == 0);
     MI.getOperand(0).setReg(X86::RSP);
     MI.getOperand(1).setReg(X86::RBP);
     MI.setDesc(TII->get(X86::LEA64r));
     Opc = X86::LEA64r;
@@ skipping 465 matching lines @@
   }
   return Modified;
 }
 
 /// createX86NaClRewritePassPass - returns an instance of the pass.
 namespace llvm {
   FunctionPass* createX86NaClRewritePass() {
     return new X86NaClRewritePass();
   }
 }