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1 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===// | 1 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file declares the InstARM32 and OperandARM32 classes and | 10 // This file declares the InstARM32 and OperandARM32 classes and |
11 // their subclasses. This represents the machine instructions and | 11 // their subclasses. This represents the machine instructions and |
12 // operands used for ARM32 code selection. | 12 // operands used for ARM32 code selection. |
13 // | 13 // |
14 //===----------------------------------------------------------------------===// | 14 //===----------------------------------------------------------------------===// |
15 | 15 |
16 #ifndef SUBZERO_SRC_ICEINSTARM32_H | 16 #ifndef SUBZERO_SRC_ICEINSTARM32_H |
17 #define SUBZERO_SRC_ICEINSTARM32_H | 17 #define SUBZERO_SRC_ICEINSTARM32_H |
18 | 18 |
19 #include "IceDefs.h" | 19 #include "IceDefs.h" |
20 #include "IceInst.h" | |
21 #include "IceInstARM32.def" | |
22 #include "IceOperand.h" | |
20 | 23 |
21 namespace Ice { | 24 namespace Ice { |
22 | 25 |
23 class TargetARM32; | 26 class TargetARM32; |
24 // Fill this in. | 27 |
28 // OperandARM32 extends the Operand hierarchy. | |
29 // TODO(jvoung): Add the OperandARM32Mem and OperandARM32Flex. | |
30 class OperandARM32 : public Operand { | |
31 OperandARM32() = delete; | |
32 OperandARM32(const OperandARM32 &) = delete; | |
33 OperandARM32 &operator=(const OperandARM32 &) = delete; | |
34 | |
35 public: | |
36 enum OperandKindARM32 { k__Start = Operand::kTarget }; | |
37 | |
38 enum ShiftKind { | |
39 kNoShift = -1, | |
40 #define X(enum, emit) enum, | |
41 ICEINSTARM32SHIFT_TABLE | |
42 #undef X | |
43 }; | |
44 | |
45 using Operand::dump; | |
46 void dump(const Cfg *, Ostream &Str) const override { | |
47 if (ALLOW_DUMP) | |
48 Str << "<OperandARM32>"; | |
49 } | |
50 | |
51 protected: | |
52 OperandARM32(OperandKindARM32 Kind, Type Ty) | |
53 : Operand(static_cast<OperandKind>(Kind), Ty) {} | |
54 ~OperandARM32() override {} | |
55 }; | |
56 | |
57 class InstARM32 : public InstTarget { | |
58 InstARM32() = delete; | |
59 InstARM32(const InstARM32 &) = delete; | |
60 InstARM32 &operator=(const InstARM32 &) = delete; | |
61 | |
62 public: | |
63 enum InstKindARM32 { k__Start = Inst::Target, Ret }; | |
64 | |
65 // TODO(jvoung): Find a better place to put some of these constants. | |
66 enum { kOffset12Bits = 12 }; | |
67 | |
68 static const char *getWidthString(Type Ty); | |
69 | |
70 void dump(const Cfg *Func) const override; | |
71 | |
72 protected: | |
73 InstARM32(Cfg *Func, InstKindARM32 Kind, SizeT Maxsrcs, Variable *Dest) | |
74 : InstTarget(Func, static_cast<InstKind>(Kind), Maxsrcs, Dest) {} | |
75 ~InstARM32() override {} | |
76 static bool isClassof(const Inst *Inst, InstKindARM32 MyKind) { | |
77 return Inst->getKind() == static_cast<InstKind>(MyKind); | |
78 } | |
79 }; | |
80 | |
81 // Ret psuedo-instruction. This is actually a "bx" instruction with | |
Jim Stichnoth
2015/05/11 20:12:31
pseudo
jvoung (off chromium)
2015/05/11 22:11:51
Done.
| |
82 // an "lr" register operand, but epilogue lowering will search for a Ret | |
Jim Stichnoth
2015/05/11 20:12:31
I'm not ecstatic about how the Ret marker stuff is
jvoung (off chromium)
2015/05/11 22:11:51
I guess LLVM would have a flag on the instruction
| |
83 // instead of a generic "bx". This instruction also takes a Source | |
84 // operand (for non-void returning functions) for liveness analysis, though | |
85 // a FakeUse before the ret would do just as well. | |
86 class InstARM32Ret : public InstARM32 { | |
87 InstARM32Ret() = delete; | |
88 InstARM32Ret(const InstARM32Ret &) = delete; | |
89 InstARM32Ret &operator=(const InstARM32Ret &) = delete; | |
90 | |
91 public: | |
92 static InstARM32Ret *create(Cfg *Func, Variable *LR, | |
93 Variable *Source = nullptr) { | |
94 return new (Func->allocate<InstARM32Ret>()) InstARM32Ret(Func, LR, Source); | |
95 } | |
96 void emit(const Cfg *Func) const override; | |
97 void emitIAS(const Cfg *Func) const override; | |
98 void dump(const Cfg *Func) const override; | |
99 static bool classof(const Inst *Inst) { return isClassof(Inst, Ret); } | |
100 | |
101 private: | |
102 InstARM32Ret(Cfg *Func, Variable *LR, Variable *Source); | |
103 ~InstARM32Ret() override {} | |
104 }; | |
25 | 105 |
26 } // end of namespace Ice | 106 } // end of namespace Ice |
27 | 107 |
28 #endif // SUBZERO_SRC_ICEINSTARM32_H | 108 #endif // SUBZERO_SRC_ICEINSTARM32_H |
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