| OLD | NEW |
|---|
| 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// | 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 // This file defines properties of ARM32 instructions in the form of x-macros. | 10 // This file defines properties of ARM32 instructions in the form of x-macros. |
| (...skipping 43 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 54 // isInt, isFP) | 54 // isInt, isFP) |
| 55 | 55 |
| 56 #define REGARM32_TABLE_BOUNDS \ | 56 #define REGARM32_TABLE_BOUNDS \ |
| 57 /* val, init */ \ | 57 /* val, init */ \ |
| 58 X(Reg_GPR_First, = Reg_r0) \ | 58 X(Reg_GPR_First, = Reg_r0) \ |
| 59 X(Reg_GPR_Last, = Reg_pc) | 59 X(Reg_GPR_Last, = Reg_pc) |
| 60 //define X(val, init) | 60 //define X(val, init) |
| 61 | 61 |
| 62 // TODO(jvoung): add condition code tables, etc. | 62 // TODO(jvoung): add condition code tables, etc. |
| 63 | 63 |
| 64 // Load/Store instruction width suffixes. |
| 65 #define ICETYPEARM32_TABLE \ |
| 66 /* tag, element type, width, addr off bits sext, zext */ \ |
| 67 X(IceType_void, IceType_void, "", 0, 0) \ |
| 68 X(IceType_i1, IceType_void, "b", 8, 12) \ |
| 69 X(IceType_i8, IceType_void, "b", 8, 12) \ |
| 70 X(IceType_i16, IceType_void, "h", 8, 8) \ |
| 71 X(IceType_i32, IceType_void, "", 12, 12) \ |
| 72 X(IceType_i64, IceType_void, "d", 8, 8) \ |
| 73 X(IceType_f32, IceType_void, "", 10, 10) \ |
| 74 X(IceType_f64, IceType_void, "", 10, 10) \ |
| 75 X(IceType_v4i1, IceType_i32 , "", 0, 0) \ |
| 76 X(IceType_v8i1, IceType_i16 , "", 0, 0) \ |
| 77 X(IceType_v16i1, IceType_i8 , "", 0, 0) \ |
| 78 X(IceType_v16i8, IceType_i8 , "", 0, 0) \ |
| 79 X(IceType_v8i16, IceType_i16 , "", 0, 0) \ |
| 80 X(IceType_v4i32, IceType_i32 , "", 0, 0) \ |
| 81 X(IceType_v4f32, IceType_f32 , "", 0, 0) \ |
| 82 //#define X(tag, elementty, width, sbits, ubits) |
| 64 | 83 |
| 65 #endif // SUBZERO_SRC_ICEINSTARM32_DEF | 84 #endif // SUBZERO_SRC_ICEINSTARM32_DEF |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 1136793002:
Handle ARM "ret void" and function alignment with proper padding. (Closed)
Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master