Roll src/third_party/boringssl/src 68de407:771a138

third_party/boringssl/linux-arm/crypto/sha/sha256-armv4.S

 
 @ ====================================================================
 @ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
 @ project. The module is, however, dual licensed under OpenSSL and
 @ CRYPTOGAMS licenses depending on where you obtain it. For further
 @ details see http://www.openssl.org/~appro/cryptogams/.
 @
 @ Permission to use under GPL terms is granted.
 @ ====================================================================
 
@@ skipping 29 matching lines @@
 # include "arm_arch.h"
 #else
 # define __ARM_ARCH__ __LINUX_ARM_ARCH__
 # define __ARM_MAX_ARCH__ 7
 #endif
 
 .text
 #if __ARM_ARCH__<7
 .code   32
 #else
-.syntax unified
-# ifdef __thumb2__
+.syntax unified
+# if defined(__thumb2__) && !defined(__APPLE__)
 #  define adrl adr
 .thumb
 # else
-.code   32
+.code   32
 # endif
 #endif
 
 .type   K256,%object
 .align  5
 K256:
 .word   0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
 .word   0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
 .word   0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
 .word   0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
 .word   0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
 .word   0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
 .word   0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
 .word   0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
 .word   0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
 .word   0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
 .word   0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
 .word   0xd192e819,0xd6990624,0xf40e3585,0x106aa070
 .word   0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
 .word   0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
 .word   0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
 .word   0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
 .size   K256,.-K256
 .word   0                               @ terminator
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
 .LOPENSSL_armcap:
-.word   OPENSSL_armcap_P-sha256_block_data_order
+.word   OPENSSL_armcap_P-.Lsha256_block_data_order
 #endif
 .align  5
 
-.global sha256_block_data_order
+.globl  sha256_block_data_order
 .type   sha256_block_data_order,%function
 sha256_block_data_order:
+.Lsha256_block_data_order:
 #if __ARM_ARCH__<7
         sub     r3,pc,#8                @ sha256_block_data_order
 #else
         adr     r3,sha256_block_data_order
 #endif
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
         ldr     r12,.LOPENSSL_armcap
         ldr     r12,[r3,r12]            @ OPENSSL_armcap_P
+#ifdef  __APPLE__
+        ldr     r12,[r12]
+#endif
         tst     r12,#ARMV8_SHA256
         bne     .LARMv8
         tst     r12,#ARMV7_NEON
         bne     .LNEON
 #endif
         add     r2,r1,r2,lsl#6  @ len to point at the end of inp
         stmdb   sp!,{r0,r1,r2,r4-r11,lr}
         ldmia   r0,{r4,r5,r6,r7,r8,r9,r10,r11}
         sub     r14,r3,#256+32  @ K256
         sub     sp,sp,#16*4             @ alloca(X[16])
@@ skipping 1743 matching lines @@
         ldr     r12,[sp,#18*4]          @ pull inp+len
         add     r10,r10,r0
         add     r11,r11,r2
         stmia   r3,{r4,r5,r6,r7,r8,r9,r10,r11}
         cmp     r1,r12
         sub     r14,r14,#256    @ rewind Ktbl
         bne     .Loop
 
         add     sp,sp,#19*4     @ destroy frame
 #if __ARM_ARCH__>=5
-        ldmia   sp!,{r4-r11,pc}
+        ldmia   sp!,{r4,r5,r6,r7,r8,r9,r10,r11,pc}
 #else
-        ldmia   sp!,{r4-r11,lr}
+        ldmia   sp!,{r4,r5,r6,r7,r8,r9,r10,r11,lr}
         tst     lr,#1
         moveq   pc,lr                   @ be binary compatible with V4, yet
-        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
+.word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
 #endif
 .size   sha256_block_data_order,.-sha256_block_data_order
 #if __ARM_MAX_ARCH__>=7
 .arch   armv7-a
 .fpu    neon
 
-.global sha256_block_data_order_neon
+.globl  sha256_block_data_order_neon
 .type   sha256_block_data_order_neon,%function
 .align  4
 sha256_block_data_order_neon:
 .LNEON:
-        stmdb   sp!,{r4-r12,lr}
+        stmdb   sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
 
         sub     r11,sp,#16*4+16
-        adrl    r14,K256
+        adr     r14,K256
         bic     r11,r11,#15             @ align for 128-bit stores
         mov     r12,sp
         mov     sp,r11                  @ alloca
         add     r2,r1,r2,lsl#6  @ len to point at the end of inp
 
-        vld1.8          {q0},[r1]!
-        vld1.8          {q1},[r1]!
-        vld1.8          {q2},[r1]!
-        vld1.8          {q3},[r1]!
-        vld1.32         {q8},[r14,:128]!
-        vld1.32         {q9},[r14,:128]!
-        vld1.32         {q10},[r14,:128]!
-        vld1.32         {q11},[r14,:128]!
+        vld1.8  {q0},[r1]!
+        vld1.8  {q1},[r1]!
+        vld1.8  {q2},[r1]!
+        vld1.8  {q3},[r1]!
+        vld1.32 {q8},[r14,:128]!
+        vld1.32 {q9},[r14,:128]!
+        vld1.32 {q10},[r14,:128]!
+        vld1.32 {q11},[r14,:128]!
         vrev32.8        q0,q0           @ yes, even on
-        str             r0,[sp,#64]
+        str     r0,[sp,#64]
         vrev32.8        q1,q1           @ big-endian
-        str             r1,[sp,#68]
-        mov             r1,sp
+        str     r1,[sp,#68]
+        mov     r1,sp
         vrev32.8        q2,q2
-        str             r2,[sp,#72]
+        str     r2,[sp,#72]
         vrev32.8        q3,q3
-        str             r12,[sp,#76]            @ save original sp
+        str     r12,[sp,#76]            @ save original sp
         vadd.i32        q8,q8,q0
         vadd.i32        q9,q9,q1
-        vst1.32         {q8},[r1,:128]!
+        vst1.32 {q8},[r1,:128]!
         vadd.i32        q10,q10,q2
-        vst1.32         {q9},[r1,:128]!
+        vst1.32 {q9},[r1,:128]!
         vadd.i32        q11,q11,q3
-        vst1.32         {q10},[r1,:128]!
-        vst1.32         {q11},[r1,:128]!
+        vst1.32 {q10},[r1,:128]!
+        vst1.32 {q11},[r1,:128]!
 
-        ldmia           r0,{r4-r11}
-        sub             r1,r1,#64
-        ldr             r2,[sp,#0]
-        eor             r12,r12,r12
-        eor             r3,r5,r6
-        b               .L_00_48
+        ldmia   r0,{r4,r5,r6,r7,r8,r9,r10,r11}
+        sub     r1,r1,#64
+        ldr     r2,[sp,#0]
+        eor     r12,r12,r12
+        eor     r3,r5,r6
+        b       .L_00_48
 
 .align  4
 .L_00_48:
         vext.8  q8,q0,q1,#4
         add     r11,r11,r2
         eor     r2,r9,r10
         eor     r0,r8,r8,ror#5
         vext.8  q9,q2,q3,#4
         add     r4,r4,r12
         and     r2,r2,r8
@@ skipping 380 matching lines @@
         and     r12,r12,r3
         add     r8,r8,r4
         vst1.32 {q8},[r1,:128]!
         add     r4,r4,r0,ror#2
         eor     r12,r12,r6
         teq     r2,#0                           @ check for K256 terminator
         ldr     r2,[sp,#0]
         sub     r1,r1,#64
         bne     .L_00_48
 
-        ldr             r1,[sp,#68]
-        ldr             r0,[sp,#72]
-        sub             r14,r14,#256    @ rewind r14
-        teq             r1,r0
-        it              eq
-        subeq           r1,r1,#64               @ avoid SEGV
-        vld1.8          {q0},[r1]!              @ load next input block
-        vld1.8          {q1},[r1]!
-        vld1.8          {q2},[r1]!
-        vld1.8          {q3},[r1]!
-        it              ne
-        strne           r1,[sp,#68]
-        mov             r1,sp
+        ldr     r1,[sp,#68]
+        ldr     r0,[sp,#72]
+        sub     r14,r14,#256    @ rewind r14
+        teq     r1,r0
+        it      eq
+        subeq   r1,r1,#64               @ avoid SEGV
+        vld1.8  {q0},[r1]!              @ load next input block
+        vld1.8  {q1},[r1]!
+        vld1.8  {q2},[r1]!
+        vld1.8  {q3},[r1]!
+        it      ne
+        strne   r1,[sp,#68]
+        mov     r1,sp
         add     r11,r11,r2
         eor     r2,r9,r10
         eor     r0,r8,r8,ror#5
         add     r4,r4,r12
         vld1.32 {q8},[r14,:128]!
         and     r2,r2,r8
         eor     r12,r0,r8,ror#19
         eor     r0,r4,r4,ror#11
         eor     r2,r2,r10
         vrev32.8        q0,q0
@@ skipping 289 matching lines @@
         add     r7,r7,r1
         ldr     r1,[r2,#28]
         add     r8,r8,r0
         str     r4,[r2],#4
         add     r9,r9,r12
         str     r5,[r2],#4
         add     r10,r10,r3
         str     r6,[r2],#4
         add     r11,r11,r1
         str     r7,[r2],#4
-        stmia   r2,{r8-r11}
+        stmia   r2,{r8,r9,r10,r11}
 
         ittte   ne
         movne   r1,sp
         ldrne   r2,[sp,#0]
         eorne   r12,r12,r12
         ldreq   sp,[sp,#76]                     @ restore original sp
         itt     ne
         eorne   r3,r5,r6
         bne     .L_00_48
 
-        ldmia   sp!,{r4-r12,pc}
+        ldmia   sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
 .size   sha256_block_data_order_neon,.-sha256_block_data_order_neon
 #endif
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
 
-# ifdef __thumb2__
+# if defined(__thumb2__) && !defined(__APPLE__)
 #  define INST(a,b,c,d) .byte   c,d|0xc,a,b
 # else
 #  define INST(a,b,c,d) .byte   a,b,c,d
 # endif
 
 .type   sha256_block_data_order_armv8,%function
 .align  5
 sha256_block_data_order_armv8:
 .LARMv8:
         vld1.32 {q0,q1},[r0]
-# ifdef __thumb2__
+# ifdef __APPLE__
+        sub     r3,r3,#256+32
+# elif  defined(__thumb2__)
         adr     r3,.LARMv8
         sub     r3,r3,#.LARMv8-K256
 # else
         adrl    r3,K256
 # endif
         add     r2,r1,r2,lsl#6  @ len to point at the end of inp
 
 .Loop_v8:
-        vld1.8          {q8-q9},[r1]!
-        vld1.8          {q10-q11},[r1]!
-        vld1.32         {q12},[r3]!
+        vld1.8  {q8,q9},[r1]!
+        vld1.8  {q10,q11},[r1]!
+        vld1.32 {q12},[r3]!
         vrev32.8        q8,q8
         vrev32.8        q9,q9
         vrev32.8        q10,q10
         vrev32.8        q11,q11
-        vmov            q14,q0  @ offload
-        vmov            q15,q1
-        teq             r1,r2
-        vld1.32         {q13},[r3]!
+        vmov    q14,q0  @ offload
+        vmov    q15,q1
+        teq     r1,r2
+        vld1.32 {q13},[r3]!
         vadd.i32        q12,q12,q8
         INST(0xe2,0x03,0xfa,0xf3)       @ sha256su0 q8,q9
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x68,0x0c,0x02,0xf3)       @ sha256h q0,q1,q12
         INST(0x68,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q12
         INST(0xe6,0x0c,0x64,0xf3)       @ sha256su1 q8,q10,q11
-        vld1.32         {q12},[r3]!
+        vld1.32 {q12},[r3]!
         vadd.i32        q13,q13,q9
         INST(0xe4,0x23,0xfa,0xf3)       @ sha256su0 q9,q10
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x6a,0x0c,0x02,0xf3)       @ sha256h q0,q1,q13
         INST(0x6a,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q13
         INST(0xe0,0x2c,0x66,0xf3)       @ sha256su1 q9,q11,q8
-        vld1.32         {q13},[r3]!
+        vld1.32 {q13},[r3]!
         vadd.i32        q12,q12,q10
         INST(0xe6,0x43,0xfa,0xf3)       @ sha256su0 q10,q11
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x68,0x0c,0x02,0xf3)       @ sha256h q0,q1,q12
         INST(0x68,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q12
         INST(0xe2,0x4c,0x60,0xf3)       @ sha256su1 q10,q8,q9
-        vld1.32         {q12},[r3]!
+        vld1.32 {q12},[r3]!
         vadd.i32        q13,q13,q11
         INST(0xe0,0x63,0xfa,0xf3)       @ sha256su0 q11,q8
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x6a,0x0c,0x02,0xf3)       @ sha256h q0,q1,q13
         INST(0x6a,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q13
         INST(0xe4,0x6c,0x62,0xf3)       @ sha256su1 q11,q9,q10
-        vld1.32         {q13},[r3]!
+        vld1.32 {q13},[r3]!
         vadd.i32        q12,q12,q8
         INST(0xe2,0x03,0xfa,0xf3)       @ sha256su0 q8,q9
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x68,0x0c,0x02,0xf3)       @ sha256h q0,q1,q12
         INST(0x68,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q12
         INST(0xe6,0x0c,0x64,0xf3)       @ sha256su1 q8,q10,q11
-        vld1.32         {q12},[r3]!
+        vld1.32 {q12},[r3]!
         vadd.i32        q13,q13,q9
         INST(0xe4,0x23,0xfa,0xf3)       @ sha256su0 q9,q10
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x6a,0x0c,0x02,0xf3)       @ sha256h q0,q1,q13
         INST(0x6a,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q13
         INST(0xe0,0x2c,0x66,0xf3)       @ sha256su1 q9,q11,q8
-        vld1.32         {q13},[r3]!
+        vld1.32 {q13},[r3]!
         vadd.i32        q12,q12,q10
         INST(0xe6,0x43,0xfa,0xf3)       @ sha256su0 q10,q11
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x68,0x0c,0x02,0xf3)       @ sha256h q0,q1,q12
         INST(0x68,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q12
         INST(0xe2,0x4c,0x60,0xf3)       @ sha256su1 q10,q8,q9
-        vld1.32         {q12},[r3]!
+        vld1.32 {q12},[r3]!
         vadd.i32        q13,q13,q11
         INST(0xe0,0x63,0xfa,0xf3)       @ sha256su0 q11,q8
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x6a,0x0c,0x02,0xf3)       @ sha256h q0,q1,q13
         INST(0x6a,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q13
         INST(0xe4,0x6c,0x62,0xf3)       @ sha256su1 q11,q9,q10
-        vld1.32         {q13},[r3]!
+        vld1.32 {q13},[r3]!
         vadd.i32        q12,q12,q8
         INST(0xe2,0x03,0xfa,0xf3)       @ sha256su0 q8,q9
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x68,0x0c,0x02,0xf3)       @ sha256h q0,q1,q12
         INST(0x68,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q12
         INST(0xe6,0x0c,0x64,0xf3)       @ sha256su1 q8,q10,q11
-        vld1.32         {q12},[r3]!
+        vld1.32 {q12},[r3]!
         vadd.i32        q13,q13,q9
         INST(0xe4,0x23,0xfa,0xf3)       @ sha256su0 q9,q10
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x6a,0x0c,0x02,0xf3)       @ sha256h q0,q1,q13
         INST(0x6a,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q13
         INST(0xe0,0x2c,0x66,0xf3)       @ sha256su1 q9,q11,q8
-        vld1.32         {q13},[r3]!
+        vld1.32 {q13},[r3]!
         vadd.i32        q12,q12,q10
         INST(0xe6,0x43,0xfa,0xf3)       @ sha256su0 q10,q11
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x68,0x0c,0x02,0xf3)       @ sha256h q0,q1,q12
         INST(0x68,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q12
         INST(0xe2,0x4c,0x60,0xf3)       @ sha256su1 q10,q8,q9
-        vld1.32         {q12},[r3]!
+        vld1.32 {q12},[r3]!
         vadd.i32        q13,q13,q11
         INST(0xe0,0x63,0xfa,0xf3)       @ sha256su0 q11,q8
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x6a,0x0c,0x02,0xf3)       @ sha256h q0,q1,q13
         INST(0x6a,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q13
         INST(0xe4,0x6c,0x62,0xf3)       @ sha256su1 q11,q9,q10
-        vld1.32         {q13},[r3]!
+        vld1.32 {q13},[r3]!
         vadd.i32        q12,q12,q8
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x68,0x0c,0x02,0xf3)       @ sha256h q0,q1,q12
         INST(0x68,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q12
 
-        vld1.32         {q12},[r3]!
+        vld1.32 {q12},[r3]!
         vadd.i32        q13,q13,q9
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x6a,0x0c,0x02,0xf3)       @ sha256h q0,q1,q13
         INST(0x6a,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q13
 
-        vld1.32         {q13},[r3]
+        vld1.32 {q13},[r3]
         vadd.i32        q12,q12,q10
-        sub             r3,r3,#256-16   @ rewind
-        vmov            q2,q0
+        sub     r3,r3,#256-16   @ rewind
+        vmov    q2,q0
         INST(0x68,0x0c,0x02,0xf3)       @ sha256h q0,q1,q12
         INST(0x68,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q12
 
         vadd.i32        q13,q13,q11
-        vmov            q2,q0
+        vmov    q2,q0
         INST(0x6a,0x0c,0x02,0xf3)       @ sha256h q0,q1,q13
         INST(0x6a,0x2c,0x14,0xf3)       @ sha256h2 q1,q2,q13
 
         vadd.i32        q0,q0,q14
         vadd.i32        q1,q1,q15
-        it              ne
-        bne             .Loop_v8
+        it      ne
+        bne     .Loop_v8
 
-        vst1.32         {q0,q1},[r0]
+        vst1.32 {q0,q1},[r0]
 
         bx      lr              @ bx lr
 .size   sha256_block_data_order_armv8,.-sha256_block_data_order_armv8
 #endif
-.asciz  "SHA256 block transform for ARMv4/NEON/ARMv8, CRYPTOGAMS by <appro@openssl.org>"
+.byte   83,72,65,50,53,54,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,47,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
+.align  2
 .align  2
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
-.comm   OPENSSL_armcap_P,4,4
-.hidden OPENSSL_armcap_P
+.comm   OPENSSL_armcap_P,4,4
+.hidden OPENSSL_armcap_P
 #endif