Update Yasm to 1.2.0 (Yasm Part 1/3)

third_party/yasm/patched-yasm/modules/arch/x86/x86id.c

 /*
  * x86 identifier recognition and instruction handling
  *
  *  Copyright (C) 2002-2007  Peter Johnson
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND OTHER CONTRIBUTORS ``AS IS''
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR OTHER CONTRIBUTORS BE
  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <ctype.h>
 #include <util.h>
-RCSID("$Id: x86id.c 2279 2010-01-19 07:57:43Z peter $");
 
 #include <libyasm.h>
 #include <libyasm/phash.h>
 
 #include "modules/arch/x86/x86arch.h"
 
 
 static const char *cpu_find_reverse(unsigned int cpu0, unsigned int cpu1,
                                     unsigned int cpu2);
 
@@ skipping 64 matching lines @@
      */
     OPT_MemOffs = 21,
     OPT_Imm1 = 22,      /* immediate, value=1 (for special-case shift) */
     /* immediate, does not contain SEG:OFF (for jmp/call) */
     OPT_ImmNotSegOff = 23,
     OPT_XMM0 = 24,      /* XMM0 */
     /* AX/EAX/RAX memory operand only (EA) [special case for SVM opcodes]
      */
     OPT_MemrAX = 25,
     /* EAX memory operand only (EA) [special case for SVM skinit opcode] */
-    OPT_MemEAX = 26
+    OPT_MemEAX = 26,
+    /* XMM VSIB memory operand */
+    OPT_MemXMMIndex = 27,
+    /* YMM VSIB memory operand */
+    OPT_MemYMMIndex = 28
 };
 
 enum x86_operand_size {
     /* any size acceptable/no size spec acceptable (dep. on strict) */
     OPS_Any = 0,
     /* 8/16/32/64/80/128/256 bits (from user or reg size) */
     OPS_8 = 1,
     OPS_16 = 2,
     OPS_32 = 3,
     OPS_64 = 4,
@@ skipping 215 matching lines @@
     x86_id_insn_finalize,
     NULL,
     yasm_bc_calc_len_common,
     yasm_bc_expand_common,
     yasm_bc_tobytes_common,
     YASM_BC_SPECIAL_INSN
 };
 
 #include "x86insns.c"
 
+/* Looks for the first SIMD register match for the purposes of VSIB matching.
+ * Full legality checking is performed in EA code.
+ */
+static int
+x86_expr_contains_simd_cb(const yasm_expr__item *ei, void *d)
+{
+    int ymm = *((int *)d);
+    if (ei->type != YASM_EXPR_REG)
+        return 0;
+    switch ((x86_expritem_reg_size)(ei->data.reg & ~0xFUL)) {
+        case X86_XMMREG:
+            if (!ymm)
+                return 1;
+            break;
+        case X86_YMMREG:
+            if (ymm)
+                return 1;
+            break;
+        default:
+            break;
+    }
+    return 0;
+}
+
+static int
+x86_expr_contains_simd(const yasm_expr *e, int ymm)
+{
+    return yasm_expr__traverse_leaves_in_const(e, &ymm,
+                                               x86_expr_contains_simd_cb);
+}
+
 static void
 x86_finalize_common(x86_common *common, const x86_insn_info *info,
                     unsigned int mode_bits)
 {
     common->addrsize = 0;
     common->opersize = info->opersize;
     common->lockrep_pre = 0;
     common->mode_bits = (unsigned char)mode_bits;
 }
 
@@ skipping 484 matching lines @@
                     break;
                 }
                 case OPT_MemEAX: {
                     const uintptr_t *regp;
                     if (op->type != YASM_INSN__OPERAND_MEMORY ||
                         !(regp = yasm_expr_get_reg(&op->data.ea->disp.abs, 0)) ||
                         *regp != (X86_REG32 | 0))
                         mismatch = 1;
                     break;
                 }
+                case OPT_MemXMMIndex:
+                    if (op->type != YASM_INSN__OPERAND_MEMORY ||
+                        !x86_expr_contains_simd(op->data.ea->disp.abs, 0))
+                        mismatch = 1;
+                    break;
+                case OPT_MemYMMIndex:
+                    if (op->type != YASM_INSN__OPERAND_MEMORY ||
+                        !x86_expr_contains_simd(op->data.ea->disp.abs, 1))
+                        mismatch = 1;
+                    break;
                 default:
                     yasm_internal_error(N_("invalid operand type"));
             }
 
             if (mismatch)
                 break;
 
             /* Check operand size */
             size = size_lookup[info_ops[i].size];
             if (id_insn->parser == X86_PARSER_GAS) {
@@ skipping 360 matching lines @@
                             yasm_internal_error(
                                 N_("invalid operand conversion"));
                         case YASM_INSN__OPERAND_MEMORY:
                             if (op->seg)
                                 yasm_error_set(YASM_ERROR_VALUE,
                                     N_("invalid segment in effective address"));
                             insn->x86_ea = (x86_effaddr *)op->data.ea;
                             if (info_ops[i].type == OPT_MemOffs)
                                 /* Special-case for MOV MemOffs instruction */
                                 yasm_x86__ea_set_disponly(insn->x86_ea);
-                            else if (id_insn->default_rel &&
-                                     !op->data.ea->not_pc_rel &&
-                                     op->data.ea->segreg != 0x6404 &&
-                                     op->data.ea->segreg != 0x6505 &&
-                                     !yasm_expr__contains(
-                                        op->data.ea->disp.abs, YASM_EXPR_REG))
+                            else if (info_ops[i].type == OPT_MemXMMIndex) {
+                                /* Remember VSIB mode */
+                                insn->x86_ea->vsib_mode = 1;
+                                insn->x86_ea->need_sib = 1;
+                            } else if (info_ops[i].type == OPT_MemYMMIndex) {
+                                /* Remember VSIB mode */
+                                insn->x86_ea->vsib_mode = 2;
+                                insn->x86_ea->need_sib = 1;
+                            } else if (id_insn->default_rel &&
+                                       !op->data.ea->not_pc_rel &&
+                                       op->data.ea->segreg != 0x6404 &&
+                                       op->data.ea->segreg != 0x6505 &&
+                                       !yasm_expr__contains(
+                                          op->data.ea->disp.abs, YASM_EXPR_REG))
                                 /* Enable default PC-rel if no regs and segreg
                                  * is not FS or GS.
                                  */
                                 insn->x86_ea->ea.pc_rel = 1;
                             break;
                         case YASM_INSN__OPERAND_IMM:
                             insn->x86_ea =
                                 yasm_x86__ea_create_imm(insn->x86_ea,
                                     op->data.val,
                                     size_lookup[info_ops[i].size]);
@@ skipping 638 matching lines @@
     id_insn->mode_bits = arch_x86->mode_bits;
     id_insn->suffix = (PARSER(arch_x86) == X86_PARSER_GAS) ? SUF_Z : 0;
     id_insn->misc_flags = 0;
     id_insn->parser = PARSER(arch_x86);
     id_insn->force_strict = arch_x86->force_strict != 0;
     id_insn->default_rel = arch_x86->default_rel != 0;
 
     return yasm_bc_create_common(&x86_id_insn_callback, id_insn, line);
 }