Restrict immediate operands to smi where only smis are supported.

runtime/vm/assembler_x64.cc

 // Copyright (c) 2012, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_X64)
 
 #include "vm/assembler.h"
 #include "vm/heap.h"
 #include "vm/memory_region.h"
@@ skipping 964 matching lines @@
 
 void Assembler::andq(Register dst, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(dst, address, REX_W);
   EmitUint8(0x23);
   EmitOperand(dst & 7, address);
 }
 
 
 void Assembler::andq(Register dst, const Immediate& imm) {
-  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitRegisterREX(dst, REX_W);
-  EmitComplex(4, Operand(dst), imm);
+  if (imm.is_int32()) {
+    AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+    EmitRegisterREX(dst, REX_W);
+    EmitComplex(4, Operand(dst), imm);
+  } else {
+    movq(TMP, imm);
+    andq(dst, TMP);
+  }
 }
 
 
 void Assembler::orq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x0B);
   EmitOperand(dst & 7, operand);
 }
 
 
 void Assembler::orq(Register dst, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(dst, address, REX_W);
   EmitUint8(0x0B);
   EmitOperand(dst & 7, address);
 }
 
 
 void Assembler::orq(Register dst, const Immediate& imm) {
-  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitRegisterREX(dst, REX_W);
-  EmitComplex(1, Operand(dst), imm);
+  if (imm.is_int32()) {
+    AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+    EmitRegisterREX(dst, REX_W);
+    EmitComplex(1, Operand(dst), imm);
+  } else {
+    movq(TMP, imm);
+    orq(dst, TMP);
+  }
 }
 
 
 void Assembler::xorq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x33);
   EmitOperand(dst & 7, operand);
 }
 
 
 void Assembler::xorq(Register dst, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(dst, address, REX_W);
   EmitUint8(0x33);
   EmitOperand(dst & 7, address);
 }
 
 
 void Assembler::xorq(const Address& dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(src, dst, REX_W);
   EmitUint8(0x31);
   EmitOperand(src & 7, dst);
 }
 
 
 void Assembler::xorq(Register dst, const Immediate& imm) {
-  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitRegisterREX(dst, REX_W);
-  EmitComplex(6, Operand(dst), imm);
+  if (imm.is_int32()) {
+    AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+    EmitRegisterREX(dst, REX_W);
+    EmitComplex(6, Operand(dst), imm);
+  } else {
+    movq(TMP, imm);
+    xorq(dst, TMP);
+  }
 }
 
 
 void Assembler::addl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_NONE);
   EmitUint8(0x03);
   EmitOperand(dst & 7, operand);
 }
@@ skipping 15 matching lines @@
   EmitOperand(dst & 7, address);
 }
 
 
 void Assembler::addl(const Address& address, const Immediate& imm) {
   UNIMPLEMENTED();
 }
 
 
 void Assembler::addq(Register reg, const Immediate& imm) {
-  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitRegisterREX(reg, REX_W);
-  EmitComplex(0, Operand(reg), imm);
+  if (imm.is_int32()) {
+    AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+    EmitRegisterREX(reg, REX_W);
+    EmitComplex(0, Operand(reg), imm);
+  } else {
+    movq(TMP, imm);
+    addq(reg, TMP);
+  }
 }
 
 
 void Assembler::addq(const Address& address, const Immediate& imm) {
   // TODO(srdjan): Implement shorter version for imm32.
   movq(TMP, imm);
   addq(address, TMP);
 }
 
 
@@ skipping 57 matching lines @@
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_NONE);
   EmitUint8(0x0F);
   EmitUint8(0xAF);
   EmitOperand(dst & 7, Operand(src));
 }
 
 
 void Assembler::imull(Register reg, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitRegisterREX(reg, REX_NONE);
+  Operand operand(reg);
+  EmitOperandREX(reg, operand, REX_NONE);
   EmitUint8(0x69);
   EmitOperand(reg & 7, Operand(reg));
   EmitImmediate(imm);
 }
 
 
 void Assembler::imulq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x0F);
   EmitUint8(0xAF);
   EmitOperand(dst & 7, operand);
 }
 
 
+void Assembler::imulq(Register reg, const Immediate& imm) {
+  if (imm.is_int32()) {
+    AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+    Operand operand(reg);
+    EmitOperandREX(reg, operand, REX_W);
+    EmitUint8(0x69);
+    EmitOperand(reg & 7, Operand(reg));
+    EmitImmediate(imm);
+  } else {
+    movq(TMP, imm);
+    imulq(reg, TMP);
+  }
+}
+
+
 void Assembler::imulq(Register dst, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(dst, address, REX_W);
   EmitUint8(0x0F);
   EmitUint8(0xAF);
   EmitOperand(dst & 7, address);
 }
 
 
 void Assembler::subq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x2B);
   EmitOperand(dst & 7, operand);
 }
 
 
 void Assembler::subq(Register reg, const Immediate& imm) {
-  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitRegisterREX(reg, REX_W);
-  EmitComplex(5, Operand(reg), imm);
+  if (imm.is_int32()) {
+    AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+    EmitRegisterREX(reg, REX_W);
+    EmitComplex(5, Operand(reg), imm);
+  } else {
+    movq(TMP, imm);
+    subq(reg, TMP);
+  }
 }
 
 
 void Assembler::subq(Register reg, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(reg, address, REX_W);
   EmitUint8(0x2B);
   EmitOperand(reg & 7, address);
 }
 
@@ skipping 864 matching lines @@
 
 const char* Assembler::XmmRegisterName(XmmRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
   return xmm_reg_names[reg];
 }
 
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_X64