MIPS64: Enable shorten-64-to-32 warning.

src/mips64/simulator-mips64.h

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 
 // Declares a Simulator for MIPS instructions if we are not generating a native
 // MIPS binary. This Simulator allows us to run and debug MIPS code generation
 // on regular desktop machines.
 // V8 calls into generated code by "calling" the CALL_GENERATED_CODE macro,
 // which will start execution in the Simulator or forwards to the real entry
@@ skipping 308 matching lines @@
 
   // Operations depending on endianness.
   // Get Double Higher / Lower word.
   inline int32_t GetDoubleHIW(double* addr);
   inline int32_t GetDoubleLOW(double* addr);
   // Set Double Higher / Lower word.
   inline int32_t SetDoubleHIW(double* addr);
   inline int32_t SetDoubleLOW(double* addr);
 
   // functions called from DecodeTypeRegister
-  void DecodeTypeRegisterCOP1(Instruction* instr, const int32_t& rs_reg,
-                              const int64_t& rs, const uint64_t& rs_u,
-                              const int32_t& rt_reg, const int64_t& rt,
-                              const uint64_t& rt_u, const int32_t& rd_reg,
-                              const int32_t& fr_reg, const int32_t& fs_reg,
-                              const int32_t& ft_reg, const int32_t& fd_reg,
+  void DecodeTypeRegisterCOP1(Instruction* instr, const int32_t rs_reg,
+                              const int64_t rs, const uint64_t rs_u,
+                              const int32_t rt_reg, const int64_t rt,
+                              const uint64_t rt_u, const int32_t rd_reg,
+                              const int32_t fr_reg, const int32_t fs_reg,
+                              const int32_t ft_reg, const int32_t fd_reg,
                               int64_t& alu_out);
 
-  void DecodeTypeRegisterCOP1X(Instruction* instr, const int32_t& fr_reg,
-                               const int32_t& fs_reg, const int32_t& ft_reg,
-                               const int32_t& fd_reg);
+  void DecodeTypeRegisterCOP1X(Instruction* instr, const int32_t fr_reg,
+                               const int32_t fs_reg, const int32_t ft_reg,
+                               const int32_t fd_reg);
 
   void DecodeTypeRegisterSPECIAL(
-      Instruction* instr, const int64_t& rs_reg, const int64_t& rs,
-      const uint64_t& rs_u, const int64_t& rt_reg, const int64_t& rt,
-      const uint64_t& rt_u, const int64_t& rd_reg, const int32_t& fr_reg,
-      const int32_t& fs_reg, const int32_t& ft_reg, const int64_t& fd_reg,
-      int64_t& i64hilo, uint64_t& u64hilo, int64_t& alu_out, bool& do_interrupt,
-      int64_t& current_pc, int64_t& next_pc, int64_t& return_addr_reg,
-      int64_t& i128resultH, int64_t& i128resultL);
+      Instruction* instr, const int32_t rs_reg, const int64_t rs,
+      const uint64_t rs_u, const int32_t rt_reg, const int64_t rt,
+      const uint64_t rt_u, const int32_t rd_reg, const int32_t fr_reg,
+      const int32_t fs_reg, const int32_t ft_reg, const int32_t fd_reg,
+      const int64_t i64hilo, const uint64_t u64hilo, const int64_t alu_out,
+      const bool do_interrupt, const int64_t current_pc, const int64_t next_pc,
+      const int32_t return_addr_reg, const int64_t i128resultH,
+      const int64_t i128resultL);
 
-  void DecodeTypeRegisterSPECIAL2(Instruction* instr, const int64_t& rd_reg,
-                                  int64_t& alu_out);
 
-  void DecodeTypeRegisterSPECIAL3(Instruction* instr, const int64_t& rt_reg,
-                                  const int64_t& rd_reg, int64_t& alu_out);
+  void DecodeTypeRegisterSPECIAL2(Instruction* instr, const int32_t rd_reg,
+                                  const int64_t alu_out);
 
-  void DecodeTypeRegisterSRsType(Instruction* instr, const int32_t& fs_reg,
-                                 const int32_t& ft_reg, const int32_t& fd_reg);
+  void DecodeTypeRegisterSPECIAL3(Instruction* instr, const int32_t rt_reg,
+                                  const int32_t rd_reg, const int64_t alu_out);
 
-  void DecodeTypeRegisterDRsType(Instruction* instr, const int32_t& fs_reg,
-                                 const int32_t& ft_reg, const int32_t& fd_reg);
+  void DecodeTypeRegisterSRsType(Instruction* instr, const int32_t fs_reg,
+                                 const int32_t ft_reg, const int32_t fd_reg);
 
-  void DecodeTypeRegisterWRsType(Instruction* instr, const int32_t& fs_reg,
-                                 const int32_t& ft_reg, const int32_t& fd_reg,
+  void DecodeTypeRegisterDRsType(Instruction* instr, const int32_t fs_reg,
+                                 const int32_t ft_reg, const int32_t fd_reg);
+
+  void DecodeTypeRegisterWRsType(Instruction* instr, const int32_t fs_reg,
+                                 const int32_t ft_reg, const int32_t fd_reg,
                                  int64_t& alu_out);
 
-  void DecodeTypeRegisterLRsType(Instruction* instr, const int32_t& fs_reg,
-                                 const int32_t& fd_reg, const int32_t& ft_reg);
+  void DecodeTypeRegisterLRsType(Instruction* instr, const int32_t fs_reg,
+                                 const int32_t fd_reg, const int32_t ft_reg);
   // Executing is handled based on the instruction type.
   void DecodeTypeRegister(Instruction* instr);
 
   // Helper function for DecodeTypeRegister.
-  void ConfigureTypeRegister(Instruction* instr,
-                             int64_t* alu_out,
-                             int64_t* i64hilo,
-                             uint64_t* u64hilo,
-                             int64_t* next_pc,
-                             int64_t* return_addr_reg,
-                             bool* do_interrupt,
-                             int64_t* result128H,
+  void ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
+                             int64_t* i64hilo, uint64_t* u64hilo,
+                             int64_t* next_pc, int* return_addr_reg,
+                             bool* do_interrupt, int64_t* result128H,
                              int64_t* result128L);
 
   void DecodeTypeImmediate(Instruction* instr);
   void DecodeTypeJump(Instruction* instr);
 
   // Used for breakpoints and traps.
   void SoftwareInterrupt(Instruction* instr);
 
   // Stop helper functions.
   bool IsWatchpoint(uint64_t code);
@@ skipping 21 matching lines @@
       V8_Fatal(__FILE__, __LINE__,
                "Eror:Unexpected %i opcode in a branch delay slot.",
                instr->OpcodeValue());
     }
     InstructionDecode(instr);
   }
 
   // ICache.
   static void CheckICache(v8::internal::HashMap* i_cache, Instruction* instr);
   static void FlushOnePage(v8::internal::HashMap* i_cache, intptr_t start,
-                           int size);
+                           size_t size);
   static CachePage* GetCachePage(v8::internal::HashMap* i_cache, void* page);
 
   enum Exception {
     none,
     kIntegerOverflow,
     kIntegerUnderflow,
     kDivideByZero,
     kNumExceptions
   };
   int16_t exceptions[kNumExceptions];
@@ skipping 59 matching lines @@
 // point.
 #define CALL_GENERATED_CODE(entry, p0, p1, p2, p3, p4)                    \
   reinterpret_cast<Object*>(Simulator::current(Isolate::Current())->Call( \
       FUNCTION_ADDR(entry), 5, reinterpret_cast<int64_t*>(p0),            \
       reinterpret_cast<int64_t*>(p1), reinterpret_cast<int64_t*>(p2),     \
       reinterpret_cast<int64_t*>(p3), reinterpret_cast<int64_t*>(p4)))
 
 
 #ifdef MIPS_ABI_N64
 #define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
-    Simulator::current(Isolate::Current())->Call( \
-        entry, 10, p0, p1, p2, p3, p4, p5, p6, p7, NULL, p8)
+  static_cast<int>(                                                           \
+      Simulator::current(Isolate::Current())                                  \
+          ->Call(entry, 10, p0, p1, p2, p3, p4, p5, p6, p7, NULL, p8))
 #else  // Must be O32 Abi.
 #define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
-    Simulator::current(Isolate::Current())->Call( \
-        entry, 10, p0, p1, p2, p3, NULL, p4, p5, p6, p7, p8)
+  static_cast<int>(                                                           \
+      Simulator::current(Isolate::Current())                                  \
+          ->Call(entry, 10, p0, p1, p2, p3, NULL, p4, p5, p6, p7, p8))
 #endif  // MIPS_ABI_N64
 
 
 // The simulator has its own stack. Thus it has a different stack limit from
 // the C-based native code.  Setting the c_limit to indicate a very small
 // stack cause stack overflow errors, since the simulator ignores the input.
 // This is unlikely to be an issue in practice, though it might cause testing
 // trouble down the line.
 class SimulatorStack : public v8::internal::AllStatic {
  public:
   static inline uintptr_t JsLimitFromCLimit(Isolate* isolate,
                                             uintptr_t c_limit) {
     return Simulator::current(isolate)->StackLimit();
   }
 
   static inline uintptr_t RegisterCTryCatch(uintptr_t try_catch_address) {
     Simulator* sim = Simulator::current(Isolate::Current());
     return sim->PushAddress(try_catch_address);
   }
 
   static inline void UnregisterCTryCatch() {
     Simulator::current(Isolate::Current())->PopAddress();
   }
 };
 
 } }  // namespace v8::internal
 
 #endif  // !defined(USE_SIMULATOR)
 #endif  // V8_MIPS_SIMULATOR_MIPS_H_