MIPS64: Enable shorten-64-to-32 warning.

src/mips64/simulator-mips64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #include "src/v8.h"
@@ skipping 764 matching lines @@
   DCHECK((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0);
   return one == two;
 }
 
 
 static uint32_t ICacheHash(void* key) {
   return static_cast<uint32_t>(reinterpret_cast<uintptr_t>(key)) >> 2;
 }
 
 
-static bool AllOnOnePage(uintptr_t start, int size) {
+static bool AllOnOnePage(uintptr_t start, size_t size) {
   intptr_t start_page = (start & ~CachePage::kPageMask);
   intptr_t end_page = ((start + size) & ~CachePage::kPageMask);
   return start_page == end_page;
 }
 
 
 void Simulator::set_last_debugger_input(char* input) {
   DeleteArray(last_debugger_input_);
   last_debugger_input_ = input;
 }
@@ skipping 27 matching lines @@
       i_cache->LookupOrInsert(page, ICacheHash(page));
   if (entry->value == NULL) {
     CachePage* new_page = new CachePage();
     entry->value = new_page;
   }
   return reinterpret_cast<CachePage*>(entry->value);
 }
 
 
 // Flush from start up to and not including start + size.
-void Simulator::FlushOnePage(v8::internal::HashMap* i_cache,
-                             intptr_t start,
-                             int size) {
+void Simulator::FlushOnePage(v8::internal::HashMap* i_cache, intptr_t start,
+                             size_t size) {
   DCHECK(size <= CachePage::kPageSize);
   DCHECK(AllOnOnePage(start, size - 1));
   DCHECK((start & CachePage::kLineMask) == 0);
   DCHECK((size & CachePage::kLineMask) == 0);
   void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask));
   int offset = (start & CachePage::kPageMask);
   CachePage* cache_page = GetCachePage(i_cache, page);
   char* valid_bytemap = cache_page->ValidityByte(offset);
   memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift);
 }
@@ skipping 302 matching lines @@
 
 
 // Runtime FP routines take up to two double arguments and zero
 // or one integer arguments. All are constructed here,
 // from a0-a3 or f12 and f13 (n64), or f14 (O32).
 void Simulator::GetFpArgs(double* x, double* y, int32_t* z) {
   if (!IsMipsSoftFloatABI) {
     const int fparg2 = (kMipsAbi == kN64) ? 13 : 14;
     *x = get_fpu_register_double(12);
     *y = get_fpu_register_double(fparg2);
-    *z = get_register(a2);
+    *z = static_cast<int32_t>(get_register(a2));
   } else {
   // TODO(plind): bad ABI stuff, refactor or remove.
     // We use a char buffer to get around the strict-aliasing rules which
     // otherwise allow the compiler to optimize away the copy.
     char buffer[sizeof(*x)];
     int32_t* reg_buffer = reinterpret_cast<int32_t*>(buffer);
 
     // Registers a0 and a1 -> x.
     reg_buffer[0] = get_register(a0);
     reg_buffer[1] = get_register(a1);
@@ skipping 455 matching lines @@
     return *ptr;
   }
   PrintF("Unaligned read at 0x%08lx, pc=0x%08" V8PRIxPTR "\n",
          addr,
          reinterpret_cast<intptr_t>(instr));
   DieOrDebug();
   return 0;
 }
 
 
-void Simulator::WriteW(int64_t addr, int value, Instruction* instr) {
+void Simulator::WriteW(int64_t addr, int32_t value, Instruction* instr) {
   if (addr >= 0 && addr < 0x400) {
     // This has to be a NULL-dereference, drop into debugger.
     PrintF("Memory write to bad address: 0x%08lx, pc=0x%08lx\n",
            addr, reinterpret_cast<intptr_t>(instr));
     DieOrDebug();
   }
   if ((addr & 0x3) == 0) {
     TraceMemWr(addr, value, WORD);
     int* ptr = reinterpret_cast<int*>(addr);
     *ptr = value;
@@ skipping 531 matching lines @@
   for (int i = 1; i < kNumExceptions; i++) {
     if (exceptions[i] != 0) {
       V8_Fatal(__FILE__, __LINE__, "Error: Exception %i raised.", i);
     }
   }
 }
 
 
 // Handle execution based on instruction types.
 
-void Simulator::ConfigureTypeRegister(Instruction* instr,
-                                      int64_t* alu_out,
-                                      int64_t* i64hilo,
-                                      uint64_t* u64hilo,
-                                      int64_t* next_pc,
-                                      int64_t* return_addr_reg,
-                                      bool* do_interrupt,
-                                      int64_t* i128resultH,
+void Simulator::ConfigureTypeRegister(Instruction* instr, int64_t* alu_out,
+                                      int64_t* i64hilo, uint64_t* u64hilo,
+                                      int64_t* next_pc, int* return_addr_reg,
+                                      bool* do_interrupt, int64_t* i128resultH,
                                       int64_t* i128resultL) {
   // Every local variable declared here needs to be const.
   // This is to make sure that changed values are sent back to
   // DecodeTypeRegister correctly.
 
   // Instruction fields.
   const Opcode   op     = instr->OpcodeFieldRaw();
-  const int64_t  rs_reg = instr->RsValue();
+  const int32_t  rs_reg = instr->RsValue();
   const int64_t  rs     = get_register(rs_reg);
   const uint64_t rs_u   = static_cast<uint64_t>(rs);
-  const int64_t  rt_reg = instr->RtValue();
+  const int32_t  rt_reg = instr->RtValue();
   const int64_t  rt     = get_register(rt_reg);
   const uint64_t rt_u   = static_cast<uint64_t>(rt);
-  const int64_t  rd_reg = instr->RdValue();
+  const int32_t  rd_reg = instr->RdValue();
   const uint64_t sa     = instr->SaValue();
 
   const int32_t  fs_reg = instr->FsValue();
 
 
   // ---------- Configuration.
   switch (op) {
     case COP1:    // Coprocessor instructions.
       switch (instr->RsFieldRaw()) {
         case CFC1:
@@ skipping 48 matching lines @@
           if (rs_reg == 0) {
             // Regular logical right shift of a word by a fixed number of
             // bits instruction. RS field is always equal to 0.
             // Sign-extend the 32-bit result.
             *alu_out = static_cast<int32_t>(static_cast<uint32_t>(rt_u) >> sa);
           } else {
             // Logical right-rotate of a word by a fixed number of bits. This
             // is special case of SRL instruction, added in MIPS32 Release 2.
             // RS field is equal to 00001.
             *alu_out = static_cast<int32_t>(
-                base::bits::RotateRight32((uint32_t)rt_u, sa));
+                base::bits::RotateRight32(static_cast<const uint32_t>(rt_u),
+                                          static_cast<const uint32_t>(sa)));
           }
           break;
         case DSRL:
           *alu_out = rt_u >> sa;
           break;
         case DSRL32:
           *alu_out = rt_u >> sa >> 32;
           break;
         case SRA:
           *alu_out = (int32_t)rt >> sa;
@@ skipping 13 matching lines @@
         case SRLV:
           if (sa == 0) {
             // Regular logical right-shift of a word by a variable number of
             // bits instruction. SA field is always equal to 0.
             *alu_out = static_cast<int32_t>((uint32_t)rt_u >> rs);
           } else {
             // Logical right-rotate of a word by a variable number of bits.
             // This is special case od SRLV instruction, added in MIPS32
             // Release 2. SA field is equal to 00001.
             *alu_out = static_cast<int32_t>(
-                base::bits::RotateRight32((uint32_t)rt_u, rs_u));
+                base::bits::RotateRight32(static_cast<const uint32_t>(rt_u),
+                                          static_cast<const uint32_t>(rs_u)));
           }
           break;
         case DSRLV:
           if (sa == 0) {
             // Regular logical right-shift of a word by a variable number of
             // bits instruction. SA field is always equal to 0.
             *alu_out = rt_u >> rs;
           } else {
             // Logical right-rotate of a word by a variable number of bits.
             // This is special case od SRLV instruction, added in MIPS32
             // Release 2. SA field is equal to 00001.
-            *alu_out = base::bits::RotateRight32(rt_u, rs_u);
+            *alu_out =
+                base::bits::RotateRight32(static_cast<const uint32_t>(rt_u),
+                                          static_cast<const uint32_t>(rs_u));
           }
           break;
         case SRAV:
           *alu_out = (int32_t)rt >> rs;
           break;
         case DSRAV:
           *alu_out = rt >> rs;
           break;
         case MFHI:  // MFHI == CLZ on R6.
           if (kArchVariant != kMips64r6) {
@@ skipping 45 matching lines @@
           if (HaveSameSign(rs, rt)) {
             if (rs > 0) {
               exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - rt);
             } else if (rs < 0) {
               exceptions[kIntegerUnderflow] = rs < (Registers::kMinValue - rt);
             }
           }
           *alu_out = rs + rt;
           break;
         case ADDU: {
-            int32_t alu32_out = rs + rt;
-            // Sign-extend result of 32bit operation into 64bit register.
-            *alu_out = static_cast<int64_t>(alu32_out);
-          }
+          int32_t alu32_out = static_cast<int32_t>(rs + rt);
+          // Sign-extend result of 32bit operation into 64bit register.
+          *alu_out = static_cast<int64_t>(alu32_out);
           break;
+        }
         case DADDU:
           *alu_out = rs + rt;
           break;
         case SUB:
         case DSUB:
           if (!HaveSameSign(rs, rt)) {
             if (rs > 0) {
               exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue + rt);
             } else if (rs < 0) {
               exceptions[kIntegerUnderflow] = rs < (Registers::kMinValue + rt);
             }
           }
           *alu_out = rs - rt;
           break;
         case SUBU: {
-            int32_t alu32_out = rs - rt;
-            // Sign-extend result of 32bit operation into 64bit register.
-            *alu_out = static_cast<int64_t>(alu32_out);
-          }
+          int32_t alu32_out = static_cast<int32_t>(rs - rt);
+          // Sign-extend result of 32bit operation into 64bit register.
+          *alu_out = static_cast<int64_t>(alu32_out);
           break;
+        }
         case DSUBU:
           *alu_out = rs - rt;
           break;
         case AND:
           *alu_out = rs & rt;
           break;
         case OR:
           *alu_out = rs | rt;
           break;
         case XOR:
@@ skipping 51 matching lines @@
       break;
     case SPECIAL2:
       switch (instr->FunctionFieldRaw()) {
         case MUL:
           // Only the lower 32 bits are kept.
           *alu_out = (int32_t)rs_u * (int32_t)rt_u;
           break;
         case CLZ:
           // MIPS32 spec: If no bits were set in GPR rs, the result written to
           // GPR rd is 32.
-          *alu_out = base::bits::CountLeadingZeros32(rs_u);
+          *alu_out =
+              base::bits::CountLeadingZeros32(static_cast<uint32_t>(rs_u));
           break;
         default:
           UNREACHABLE();
       }
       break;
     case SPECIAL3:
       switch (instr->FunctionFieldRaw()) {
         case INS: {   // Mips32r2 instruction.
           // Interpret rd field as 5-bit msb of insert.
           uint16_t msb = rd_reg;
@@ skipping 84 matching lines @@
           UNREACHABLE();
       }
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterSRsType(Instruction* instr,
-                                          const int32_t& fs_reg,
-                                          const int32_t& ft_reg,
-                                          const int32_t& fd_reg) {
+                                          const int32_t fs_reg,
+                                          const int32_t ft_reg,
+                                          const int32_t fd_reg) {
   float fs, ft, fd;
   fs = get_fpu_register_float(fs_reg);
   ft = get_fpu_register_float(ft_reg);
   fd = get_fpu_register_float(fd_reg);
   int32_t ft_int = bit_cast<int32_t>(ft);
   int32_t fd_int = bit_cast<int32_t>(fd);
   uint32_t cc, fcsr_cc;
   cc = instr->FCccValue();
   fcsr_cc = get_fcsr_condition_bit(cc);
   switch (instr->FunctionFieldRaw()) {
@@ skipping 379 matching lines @@
     }
     default:
       // TRUNC_W_S ROUND_W_S ROUND_L_S FLOOR_W_S FLOOR_L_S
       // CEIL_W_S CEIL_L_S CVT_PS_S are unimplemented.
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterDRsType(Instruction* instr,
-                                          const int32_t& fs_reg,
-                                          const int32_t& ft_reg,
-                                          const int32_t& fd_reg) {
+                                          const int32_t fs_reg,
+                                          const int32_t ft_reg,
+                                          const int32_t fd_reg) {
   double ft, fs, fd;
   uint32_t cc, fcsr_cc;
   fs = get_fpu_register_double(fs_reg);
   ft = (instr->FunctionFieldRaw() != MOVF) ? get_fpu_register_double(ft_reg)
                                            : 0.0;
   fd = get_fpu_register_double(fd_reg);
   cc = instr->FCccValue();
   fcsr_cc = get_fcsr_condition_bit(cc);
   int64_t ft_int = bit_cast<int64_t>(ft);
   int64_t fd_int = bit_cast<int64_t>(fd);
@@ skipping 376 matching lines @@
       set_fcsr_bit(fcsr_cc, false);
       break;
     }
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterWRsType(Instruction* instr,
-                                          const int32_t& fs_reg,
-                                          const int32_t& fd_reg,
-                                          const int32_t& ft_reg,
+                                          const int32_t fs_reg,
+                                          const int32_t fd_reg,
+                                          const int32_t ft_reg,
                                           int64_t& alu_out) {
   float fs = get_fpu_register_float(fs_reg);
   float ft = get_fpu_register_float(ft_reg);
   switch (instr->FunctionFieldRaw()) {
     case CVT_S_W:  // Convert word to float (single).
       alu_out = get_fpu_register_signed_word(fs_reg);
       set_fpu_register_float(fd_reg, static_cast<float>(alu_out));
       break;
     case CVT_D_W:  // Convert word to double.
       alu_out = get_fpu_register_signed_word(fs_reg);
@@ skipping 72 matching lines @@
         set_fpu_register_word(fd_reg, 0);
       }
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterLRsType(Instruction* instr,
-                                          const int32_t& fs_reg,
-                                          const int32_t& fd_reg,
-                                          const int32_t& ft_reg) {
+                                          const int32_t fs_reg,
+                                          const int32_t fd_reg,
+                                          const int32_t ft_reg) {
   double fs = get_fpu_register_double(fs_reg);
   double ft = get_fpu_register_double(ft_reg);
   int64_t i64;
   switch (instr->FunctionFieldRaw()) {
     case CVT_D_L:  // Mips32r2 instruction.
       i64 = get_fpu_register(fs_reg);
       set_fpu_register_double(fd_reg, static_cast<double>(i64));
       break;
     case CVT_S_L:
       i64 = get_fpu_register(fs_reg);
@@ skipping 70 matching lines @@
         set_fpu_register(fd_reg, -1);
       } else {
         set_fpu_register(fd_reg, 0);
       }
       break;
     default:
       UNREACHABLE();
   }
 }
 
-
 void Simulator::DecodeTypeRegisterCOP1(
-    Instruction* instr, const int32_t& rs_reg, const int64_t& rs,
-    const uint64_t& rs_u, const int32_t& rt_reg, const int64_t& rt,
-    const uint64_t& rt_u, const int32_t& rd_reg, const int32_t& fr_reg,
-    const int32_t& fs_reg, const int32_t& ft_reg, const int32_t& fd_reg,
+    Instruction* instr, const int32_t rs_reg, const int64_t rs,
+    const uint64_t rs_u, const int32_t rt_reg, const int64_t rt,
+    const uint64_t rt_u, const int32_t rd_reg, const int32_t fr_reg,
+    const int32_t fs_reg, const int32_t ft_reg, const int32_t fd_reg,
     int64_t& alu_out) {
   switch (instr->RsFieldRaw()) {
     case BC1:  // Branch on coprocessor condition.
     case BC1EQZ:
     case BC1NEZ:
       UNREACHABLE();
       break;
     case CFC1:
       set_register(rt_reg, alu_out);
       break;
     case MFC1:
     case DMFC1:
     case MFHC1:
       set_register(rt_reg, alu_out);
       break;
     case CTC1:
       // At the moment only FCSR is supported.
       DCHECK(fs_reg == kFCSRRegister);
-      FCSR_ = registers_[rt_reg];
+      FCSR_ = static_cast<uint32_t>(registers_[rt_reg]);
       break;
     case MTC1:
       // Hardware writes upper 32-bits to zero on mtc1.
       set_fpu_register_hi_word(fs_reg, 0);
-      set_fpu_register_word(fs_reg, registers_[rt_reg]);
+      set_fpu_register_word(fs_reg, static_cast<int32_t>(registers_[rt_reg]));
       break;
     case DMTC1:
       set_fpu_register(fs_reg, registers_[rt_reg]);
       break;
     case MTHC1:
-      set_fpu_register_hi_word(fs_reg, registers_[rt_reg]);
+      set_fpu_register_hi_word(fs_reg,
+                               static_cast<int32_t>(registers_[rt_reg]));
       break;
     case S:
       DecodeTypeRegisterSRsType(instr, fs_reg, ft_reg, fd_reg);
       break;
     case D:
       DecodeTypeRegisterDRsType(instr, fs_reg, ft_reg, fd_reg);
       break;
     case W:
       DecodeTypeRegisterWRsType(instr, fs_reg, fd_reg, ft_reg, alu_out);
       break;
     case L:
       DecodeTypeRegisterLRsType(instr, fs_reg, fd_reg, ft_reg);
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterCOP1X(Instruction* instr,
-                                        const int32_t& fr_reg,
-                                        const int32_t& fs_reg,
-                                        const int32_t& ft_reg,
-                                        const int32_t& fd_reg) {
+                                        const int32_t fr_reg,
+                                        const int32_t fs_reg,
+                                        const int32_t ft_reg,
+                                        const int32_t fd_reg) {
   switch (instr->FunctionFieldRaw()) {
     case MADD_D:
       double fr, ft, fs;
       fr = get_fpu_register_double(fr_reg);
       fs = get_fpu_register_double(fs_reg);
       ft = get_fpu_register_double(ft_reg);
       set_fpu_register_double(fd_reg, fs * ft + fr);
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterSPECIAL(
-    Instruction* instr, const int64_t& rs_reg, const int64_t& rs,
-    const uint64_t& rs_u, const int64_t& rt_reg, const int64_t& rt,
-    const uint64_t& rt_u, const int64_t& rd_reg, const int32_t& fr_reg,
-    const int32_t& fs_reg, const int32_t& ft_reg, const int64_t& fd_reg,
-    int64_t& i64hilo, uint64_t& u64hilo, int64_t& alu_out, bool& do_interrupt,
-    int64_t& current_pc, int64_t& next_pc, int64_t& return_addr_reg,
-    int64_t& i128resultH, int64_t& i128resultL) {
+    Instruction* instr, const int32_t rs_reg, const int64_t rs,
+    const uint64_t rs_u, const int32_t rt_reg, const int64_t rt,
+    const uint64_t rt_u, const int32_t rd_reg, const int32_t fr_reg,
+    const int32_t fs_reg, const int32_t ft_reg, const int32_t fd_reg,
+    const int64_t i64hilo, const uint64_t u64hilo, const int64_t alu_out,
+    const bool do_interrupt, const int64_t current_pc, const int64_t next_pc,
+    const int32_t return_addr_reg, const int64_t i128resultH,
+    const int64_t i128resultL) {
   switch (instr->FunctionFieldRaw()) {
     case SELEQZ_S:
       DCHECK(kArchVariant == kMips64r6);
       set_register(rd_reg, rt == 0 ? rs : 0);
       break;
     case SELNEZ_S:
       DCHECK(kArchVariant == kMips64r6);
       set_register(rd_reg, rt != 0 ? rs : 0);
       break;
     case JR: {
@@ skipping 143 matching lines @@
       }
       break;
     default:  // For other special opcodes we do the default operation.
       set_register(rd_reg, alu_out);
       TraceRegWr(alu_out);
   }
 }
 
 
 void Simulator::DecodeTypeRegisterSPECIAL2(Instruction* instr,
-                                           const int64_t& rd_reg,
-                                           int64_t& alu_out) {
+                                           const int32_t rd_reg,
+                                           int64_t alu_out) {
   switch (instr->FunctionFieldRaw()) {
     case MUL:
       set_register(rd_reg, alu_out);
       TraceRegWr(alu_out);
       // HI and LO are UNPREDICTABLE after the operation.
       set_register(LO, Unpredictable);
       set_register(HI, Unpredictable);
       break;
     default:  // For other special2 opcodes we do the default operation.
       set_register(rd_reg, alu_out);
   }
 }
 
 
 void Simulator::DecodeTypeRegisterSPECIAL3(Instruction* instr,
-                                           const int64_t& rt_reg,
-                                           const int64_t& rd_reg,
-                                           int64_t& alu_out) {
+                                           const int32_t rt_reg,
+                                           const int32_t rd_reg,
+                                           const int64_t alu_out) {
   switch (instr->FunctionFieldRaw()) {
     case INS:
       // Ins instr leaves result in Rt, rather than Rd.
       set_register(rt_reg, alu_out);
       TraceRegWr(alu_out);
       break;
     case EXT:
     case DEXT:
       // Dext/Ext instr leaves result in Rt, rather than Rd.
       set_register(rt_reg, alu_out);
       TraceRegWr(alu_out);
       break;
     case BITSWAP:
     case DBITSWAP:
       set_register(rd_reg, alu_out);
       TraceRegWr(alu_out);
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegister(Instruction* instr) {
   // Instruction fields.
   const Opcode   op     = instr->OpcodeFieldRaw();
-  const int64_t  rs_reg = instr->RsValue();
+  const int32_t  rs_reg = instr->RsValue();
   const int64_t  rs     = get_register(rs_reg);
   const uint64_t rs_u   = static_cast<uint32_t>(rs);
-  const int64_t  rt_reg = instr->RtValue();
+  const int32_t  rt_reg = instr->RtValue();
   const int64_t  rt     = get_register(rt_reg);
   const uint64_t rt_u   = static_cast<uint32_t>(rt);
-  const int64_t  rd_reg = instr->RdValue();
+  const int32_t  rd_reg = instr->RdValue();
 
   const int32_t fr_reg = instr->FrValue();
   const int32_t fs_reg = instr->FsValue();
   const int32_t ft_reg = instr->FtValue();
   const int32_t fd_reg = instr->FdValue();
   int64_t  i64hilo = 0;
   uint64_t u64hilo = 0;
 
   // ALU output.
   // It should not be used as is. Instructions using it should always
   // initialize it first.
   int64_t alu_out = 0x12345678;
 
   // For break and trap instructions.
   bool do_interrupt = false;
 
   // For jr and jalr.
   // Get current pc.
   int64_t current_pc = get_pc();
   // Next pc
   int64_t next_pc = 0;
-  int64_t return_addr_reg = 31;
+  int32_t return_addr_reg = 31;
 
   int64_t i128resultH;
   int64_t i128resultL;
 
   // Set up the variables if needed before executing the instruction.
   ConfigureTypeRegister(instr,
                         &alu_out,
                         &i64hilo,
                         &u64hilo,
                         &next_pc,
@@ skipping 35 matching lines @@
   }
 }
 
 
 // Type 2: instructions using a 16 bytes immediate. (e.g. addi, beq).
 void Simulator::DecodeTypeImmediate(Instruction* instr) {
   // Instruction fields.
   Opcode   op     = instr->OpcodeFieldRaw();
   int64_t  rs     = get_register(instr->RsValue());
   uint64_t rs_u   = static_cast<uint64_t>(rs);
-  int64_t  rt_reg = instr->RtValue();  // Destination register.
+  int32_t  rt_reg = instr->RtValue();  // Destination register.
   int64_t  rt     = get_register(rt_reg);
   int16_t  imm16  = instr->Imm16Value();
 
   int32_t  ft_reg = instr->FtValue();  // Destination register.
   int64_t  ft     = get_fpu_register(ft_reg);
 
   // Zero extended immediate.
   uint64_t oe_imm16 = 0xffff & imm16;
   // Sign extended immediate.
   int64_t se_imm16 = imm16;
@@ skipping 122 matching lines @@
         if (rs > 0) {
           exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - se_imm16);
         } else if (rs < 0) {
           exceptions[kIntegerUnderflow] =
               rs < (Registers::kMinValue - se_imm16);
         }
       }
       alu_out = rs + se_imm16;
       break;
     case ADDIU: {
-        int32_t alu32_out = rs + se_imm16;
-        // Sign-extend result of 32bit operation into 64bit register.
-        alu_out = static_cast<int64_t>(alu32_out);
-      }
+      int32_t alu32_out = static_cast<int32_t>(rs + se_imm16);
+      // Sign-extend result of 32bit operation into 64bit register.
+      alu_out = static_cast<int64_t>(alu32_out);
       break;
+    }
     case DADDIU:
       alu_out = rs + se_imm16;
       break;
     case SLTI:
       alu_out = (rs < se_imm16) ? 1 : 0;
       break;
     case SLTIU:
       alu_out = (rs_u < static_cast<uint64_t>(se_imm16)) ? 1 : 0;
       break;
     case ANDI:
-        alu_out = rs & oe_imm16;
+      alu_out = rs & oe_imm16;
       break;
     case ORI:
-        alu_out = rs | oe_imm16;
+      alu_out = rs | oe_imm16;
       break;
     case XORI:
-        alu_out = rs ^ oe_imm16;
+      alu_out = rs ^ oe_imm16;
       break;
     case LUI: {
-        int32_t alu32_out = (oe_imm16 << 16);
-        // Sign-extend result of 32bit operation into 64bit register.
-        alu_out = static_cast<int64_t>(alu32_out);
-      }
+      int32_t alu32_out = static_cast<int32_t>(oe_imm16 << 16);
+      // Sign-extend result of 32bit operation into 64bit register.
+      alu_out = static_cast<int64_t>(alu32_out);
       break;
+    }
     // ------------- Memory instructions.
     case LB:
       addr = rs + se_imm16;
       alu_out = ReadB(addr);
       break;
     case LH:
       addr = rs + se_imm16;
       alu_out = ReadH(addr, instr);
       break;
     case LWL: {
@@ skipping 129 matching lines @@
     case LWR:
       set_register(rt_reg, alu_out);
       break;
     case SB:
       WriteB(addr, static_cast<int8_t>(rt));
       break;
     case SH:
       WriteH(addr, static_cast<uint16_t>(rt), instr);
       break;
     case SWL:
-      WriteW(addr, mem_value, instr);
+      WriteW(addr, static_cast<int32_t>(mem_value), instr);
       break;
     case SW:
-      WriteW(addr, rt, instr);
+      WriteW(addr, static_cast<int32_t>(rt), instr);
       break;
     case SD:
       Write2W(addr, rt, instr);
       break;
     case SWR:
-      WriteW(addr, mem_value, instr);
+      WriteW(addr, static_cast<int32_t>(mem_value), instr);
       break;
     case LWC1:
       set_fpu_register(ft_reg, kFPUInvalidResult);  // Trash upper 32 bits.
       set_fpu_register_word(ft_reg, static_cast<int32_t>(alu_out));
       break;
     case LDC1:
       set_fpu_register_double(ft_reg, fp_out);
       break;
     case SWC1:
       addr = rs + se_imm16;
-      WriteW(addr, get_fpu_register(ft_reg), instr);
+      WriteW(addr, static_cast<int32_t>(get_fpu_register(ft_reg)), instr);
       break;
     case SDC1:
       addr = rs + se_imm16;
       WriteD(addr, get_fpu_register_double(ft_reg), instr);
       break;
     default:
       break;
   }
 
 
@@ skipping 274 matching lines @@
 }
 
 
 #undef UNSUPPORTED
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_MIPS64