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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "src/compiler/code-generator.h" | 5 #include "src/compiler/code-generator.h" |
6 #include "src/compiler/code-generator-impl.h" | 6 #include "src/compiler/code-generator-impl.h" |
7 #include "src/compiler/gap-resolver.h" | 7 #include "src/compiler/gap-resolver.h" |
8 #include "src/compiler/node-matchers.h" | 8 #include "src/compiler/node-matchers.h" |
9 #include "src/mips/macro-assembler-mips.h" | 9 #include "src/mips/macro-assembler-mips.h" |
10 #include "src/scopes.h" | 10 #include "src/scopes.h" |
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303 #define ASSEMBLE_CHECKED_LOAD_FLOAT(width, asm_instr) \ | 303 #define ASSEMBLE_CHECKED_LOAD_FLOAT(width, asm_instr) \ |
304 do { \ | 304 do { \ |
305 auto result = i.Output##width##Register(); \ | 305 auto result = i.Output##width##Register(); \ |
306 auto ool = new (zone()) OutOfLineLoad##width(this, result); \ | 306 auto ool = new (zone()) OutOfLineLoad##width(this, result); \ |
307 if (instr->InputAt(0)->IsRegister()) { \ | 307 if (instr->InputAt(0)->IsRegister()) { \ |
308 auto offset = i.InputRegister(0); \ | 308 auto offset = i.InputRegister(0); \ |
309 __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \ | 309 __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \ |
310 __ Daddu(at, i.InputRegister(2), offset); \ | 310 __ Daddu(at, i.InputRegister(2), offset); \ |
311 __ asm_instr(result, MemOperand(at, 0)); \ | 311 __ asm_instr(result, MemOperand(at, 0)); \ |
312 } else { \ | 312 } else { \ |
313 auto offset = i.InputOperand(0).immediate(); \ | 313 int offset = static_cast<int>(i.InputOperand(0).immediate()); \ |
314 __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \ | 314 __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \ |
315 __ asm_instr(result, MemOperand(i.InputRegister(2), offset)); \ | 315 __ asm_instr(result, MemOperand(i.InputRegister(2), offset)); \ |
316 } \ | 316 } \ |
317 __ bind(ool->exit()); \ | 317 __ bind(ool->exit()); \ |
318 } while (0) | 318 } while (0) |
319 | 319 |
320 | 320 |
321 #define ASSEMBLE_CHECKED_LOAD_INTEGER(asm_instr) \ | 321 #define ASSEMBLE_CHECKED_LOAD_INTEGER(asm_instr) \ |
322 do { \ | 322 do { \ |
323 auto result = i.OutputRegister(); \ | 323 auto result = i.OutputRegister(); \ |
324 auto ool = new (zone()) OutOfLineLoadInteger(this, result); \ | 324 auto ool = new (zone()) OutOfLineLoadInteger(this, result); \ |
325 if (instr->InputAt(0)->IsRegister()) { \ | 325 if (instr->InputAt(0)->IsRegister()) { \ |
326 auto offset = i.InputRegister(0); \ | 326 auto offset = i.InputRegister(0); \ |
327 __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \ | 327 __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \ |
328 __ Daddu(at, i.InputRegister(2), offset); \ | 328 __ Daddu(at, i.InputRegister(2), offset); \ |
329 __ asm_instr(result, MemOperand(at, 0)); \ | 329 __ asm_instr(result, MemOperand(at, 0)); \ |
330 } else { \ | 330 } else { \ |
331 auto offset = i.InputOperand(0).immediate(); \ | 331 int offset = static_cast<int>(i.InputOperand(0).immediate()); \ |
332 __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \ | 332 __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \ |
333 __ asm_instr(result, MemOperand(i.InputRegister(2), offset)); \ | 333 __ asm_instr(result, MemOperand(i.InputRegister(2), offset)); \ |
334 } \ | 334 } \ |
335 __ bind(ool->exit()); \ | 335 __ bind(ool->exit()); \ |
336 } while (0) | 336 } while (0) |
337 | 337 |
338 | 338 |
339 #define ASSEMBLE_CHECKED_STORE_FLOAT(width, asm_instr) \ | 339 #define ASSEMBLE_CHECKED_STORE_FLOAT(width, asm_instr) \ |
340 do { \ | 340 do { \ |
341 Label done; \ | 341 Label done; \ |
342 if (instr->InputAt(0)->IsRegister()) { \ | 342 if (instr->InputAt(0)->IsRegister()) { \ |
343 auto offset = i.InputRegister(0); \ | 343 auto offset = i.InputRegister(0); \ |
344 auto value = i.Input##width##Register(2); \ | 344 auto value = i.Input##width##Register(2); \ |
345 __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \ | 345 __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \ |
346 __ Daddu(at, i.InputRegister(3), offset); \ | 346 __ Daddu(at, i.InputRegister(3), offset); \ |
347 __ asm_instr(value, MemOperand(at, 0)); \ | 347 __ asm_instr(value, MemOperand(at, 0)); \ |
348 } else { \ | 348 } else { \ |
349 auto offset = i.InputOperand(0).immediate(); \ | 349 int offset = static_cast<int>(i.InputOperand(0).immediate()); \ |
350 auto value = i.Input##width##Register(2); \ | 350 auto value = i.Input##width##Register(2); \ |
351 __ Branch(&done, ls, i.InputRegister(1), Operand(offset)); \ | 351 __ Branch(&done, ls, i.InputRegister(1), Operand(offset)); \ |
352 __ asm_instr(value, MemOperand(i.InputRegister(3), offset)); \ | 352 __ asm_instr(value, MemOperand(i.InputRegister(3), offset)); \ |
353 } \ | 353 } \ |
354 __ bind(&done); \ | 354 __ bind(&done); \ |
355 } while (0) | 355 } while (0) |
356 | 356 |
357 | 357 |
358 #define ASSEMBLE_CHECKED_STORE_INTEGER(asm_instr) \ | 358 #define ASSEMBLE_CHECKED_STORE_INTEGER(asm_instr) \ |
359 do { \ | 359 do { \ |
360 Label done; \ | 360 Label done; \ |
361 if (instr->InputAt(0)->IsRegister()) { \ | 361 if (instr->InputAt(0)->IsRegister()) { \ |
362 auto offset = i.InputRegister(0); \ | 362 auto offset = i.InputRegister(0); \ |
363 auto value = i.InputRegister(2); \ | 363 auto value = i.InputRegister(2); \ |
364 __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \ | 364 __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \ |
365 __ Daddu(at, i.InputRegister(3), offset); \ | 365 __ Daddu(at, i.InputRegister(3), offset); \ |
366 __ asm_instr(value, MemOperand(at, 0)); \ | 366 __ asm_instr(value, MemOperand(at, 0)); \ |
367 } else { \ | 367 } else { \ |
368 auto offset = i.InputOperand(0).immediate(); \ | 368 int offset = static_cast<int>(i.InputOperand(0).immediate()); \ |
369 auto value = i.InputRegister(2); \ | 369 auto value = i.InputRegister(2); \ |
370 __ Branch(&done, ls, i.InputRegister(1), Operand(offset)); \ | 370 __ Branch(&done, ls, i.InputRegister(1), Operand(offset)); \ |
371 __ asm_instr(value, MemOperand(i.InputRegister(3), offset)); \ | 371 __ asm_instr(value, MemOperand(i.InputRegister(3), offset)); \ |
372 } \ | 372 } \ |
373 __ bind(&done); \ | 373 __ bind(&done); \ |
374 } while (0) | 374 } while (0) |
375 | 375 |
376 | 376 |
377 #define ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(asm_instr, operation) \ | 377 #define ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(asm_instr, operation) \ |
378 do { \ | 378 do { \ |
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552 case kMips64Xor: | 552 case kMips64Xor: |
553 __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 553 __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); |
554 break; | 554 break; |
555 case kMips64Clz: | 555 case kMips64Clz: |
556 __ Clz(i.OutputRegister(), i.InputRegister(0)); | 556 __ Clz(i.OutputRegister(), i.InputRegister(0)); |
557 break; | 557 break; |
558 case kMips64Shl: | 558 case kMips64Shl: |
559 if (instr->InputAt(1)->IsRegister()) { | 559 if (instr->InputAt(1)->IsRegister()) { |
560 __ sllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); | 560 __ sllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); |
561 } else { | 561 } else { |
562 int32_t imm = i.InputOperand(1).immediate(); | 562 int64_t imm = i.InputOperand(1).immediate(); |
563 __ sll(i.OutputRegister(), i.InputRegister(0), imm); | 563 __ sll(i.OutputRegister(), i.InputRegister(0), |
| 564 static_cast<uint16_t>(imm)); |
564 } | 565 } |
565 break; | 566 break; |
566 case kMips64Shr: | 567 case kMips64Shr: |
567 if (instr->InputAt(1)->IsRegister()) { | 568 if (instr->InputAt(1)->IsRegister()) { |
568 __ srlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); | 569 __ srlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); |
569 } else { | 570 } else { |
570 int32_t imm = i.InputOperand(1).immediate(); | 571 int64_t imm = i.InputOperand(1).immediate(); |
571 __ srl(i.OutputRegister(), i.InputRegister(0), imm); | 572 __ srl(i.OutputRegister(), i.InputRegister(0), |
| 573 static_cast<uint16_t>(imm)); |
572 } | 574 } |
573 break; | 575 break; |
574 case kMips64Sar: | 576 case kMips64Sar: |
575 if (instr->InputAt(1)->IsRegister()) { | 577 if (instr->InputAt(1)->IsRegister()) { |
576 __ srav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); | 578 __ srav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); |
577 } else { | 579 } else { |
578 int32_t imm = i.InputOperand(1).immediate(); | 580 int64_t imm = i.InputOperand(1).immediate(); |
579 __ sra(i.OutputRegister(), i.InputRegister(0), imm); | 581 __ sra(i.OutputRegister(), i.InputRegister(0), |
| 582 static_cast<uint16_t>(imm)); |
580 } | 583 } |
581 break; | 584 break; |
582 case kMips64Ext: | 585 case kMips64Ext: |
583 __ Ext(i.OutputRegister(), i.InputRegister(0), i.InputInt8(1), | 586 __ Ext(i.OutputRegister(), i.InputRegister(0), i.InputInt8(1), |
584 i.InputInt8(2)); | 587 i.InputInt8(2)); |
585 break; | 588 break; |
586 case kMips64Dext: | 589 case kMips64Dext: |
587 __ Dext(i.OutputRegister(), i.InputRegister(0), i.InputInt8(1), | 590 __ Dext(i.OutputRegister(), i.InputRegister(0), i.InputInt8(1), |
588 i.InputInt8(2)); | 591 i.InputInt8(2)); |
589 break; | 592 break; |
590 case kMips64Dshl: | 593 case kMips64Dshl: |
591 if (instr->InputAt(1)->IsRegister()) { | 594 if (instr->InputAt(1)->IsRegister()) { |
592 __ dsllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); | 595 __ dsllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); |
593 } else { | 596 } else { |
594 int32_t imm = i.InputOperand(1).immediate(); | 597 int64_t imm = i.InputOperand(1).immediate(); |
595 if (imm < 32) { | 598 if (imm < 32) { |
596 __ dsll(i.OutputRegister(), i.InputRegister(0), imm); | 599 __ dsll(i.OutputRegister(), i.InputRegister(0), |
| 600 static_cast<uint16_t>(imm)); |
597 } else { | 601 } else { |
598 __ dsll32(i.OutputRegister(), i.InputRegister(0), imm - 32); | 602 __ dsll32(i.OutputRegister(), i.InputRegister(0), |
| 603 static_cast<uint16_t>(imm - 32)); |
599 } | 604 } |
600 } | 605 } |
601 break; | 606 break; |
602 case kMips64Dshr: | 607 case kMips64Dshr: |
603 if (instr->InputAt(1)->IsRegister()) { | 608 if (instr->InputAt(1)->IsRegister()) { |
604 __ dsrlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); | 609 __ dsrlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); |
605 } else { | 610 } else { |
606 int32_t imm = i.InputOperand(1).immediate(); | 611 int64_t imm = i.InputOperand(1).immediate(); |
607 if (imm < 32) { | 612 if (imm < 32) { |
608 __ dsrl(i.OutputRegister(), i.InputRegister(0), imm); | 613 __ dsrl(i.OutputRegister(), i.InputRegister(0), |
| 614 static_cast<uint16_t>(imm)); |
609 } else { | 615 } else { |
610 __ dsrl32(i.OutputRegister(), i.InputRegister(0), imm - 32); | 616 __ dsrl32(i.OutputRegister(), i.InputRegister(0), |
| 617 static_cast<uint16_t>(imm - 32)); |
611 } | 618 } |
612 } | 619 } |
613 break; | 620 break; |
614 case kMips64Dsar: | 621 case kMips64Dsar: |
615 if (instr->InputAt(1)->IsRegister()) { | 622 if (instr->InputAt(1)->IsRegister()) { |
616 __ dsrav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); | 623 __ dsrav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); |
617 } else { | 624 } else { |
618 int32_t imm = i.InputOperand(1).immediate(); | 625 int64_t imm = i.InputOperand(1).immediate(); |
619 if (imm < 32) { | 626 if (imm < 32) { |
620 __ dsra(i.OutputRegister(), i.InputRegister(0), imm); | 627 __ dsra(i.OutputRegister(), i.InputRegister(0), imm); |
621 } else { | 628 } else { |
622 __ dsra32(i.OutputRegister(), i.InputRegister(0), imm - 32); | 629 __ dsra32(i.OutputRegister(), i.InputRegister(0), imm - 32); |
623 } | 630 } |
624 } | 631 } |
625 break; | 632 break; |
626 case kMips64Ror: | 633 case kMips64Ror: |
627 __ Ror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 634 __ Ror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); |
628 break; | 635 break; |
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1089 } | 1096 } |
1090 | 1097 |
1091 | 1098 |
1092 void CodeGenerator::AssembleArchTableSwitch(Instruction* instr) { | 1099 void CodeGenerator::AssembleArchTableSwitch(Instruction* instr) { |
1093 MipsOperandConverter i(this, instr); | 1100 MipsOperandConverter i(this, instr); |
1094 Register input = i.InputRegister(0); | 1101 Register input = i.InputRegister(0); |
1095 size_t const case_count = instr->InputCount() - 2; | 1102 size_t const case_count = instr->InputCount() - 2; |
1096 Label here; | 1103 Label here; |
1097 | 1104 |
1098 __ Branch(GetLabel(i.InputRpo(1)), hs, input, Operand(case_count)); | 1105 __ Branch(GetLabel(i.InputRpo(1)), hs, input, Operand(case_count)); |
1099 __ BlockTrampolinePoolFor(case_count * 2 + 7); | 1106 __ BlockTrampolinePoolFor(static_cast<int>(case_count) * 2 + 7); |
1100 // Ensure that dd-ed labels use 8 byte aligned addresses. | 1107 // Ensure that dd-ed labels use 8 byte aligned addresses. |
1101 if ((masm()->pc_offset() & 7) != 0) { | 1108 if ((masm()->pc_offset() & 7) != 0) { |
1102 __ nop(); | 1109 __ nop(); |
1103 } | 1110 } |
1104 __ bal(&here); | 1111 __ bal(&here); |
1105 __ dsll(at, input, 3); // Branch delay slot. | 1112 __ dsll(at, input, 3); // Branch delay slot. |
1106 __ bind(&here); | 1113 __ bind(&here); |
1107 __ daddu(at, at, ra); | 1114 __ daddu(at, at, ra); |
1108 __ ld(at, MemOperand(at, 4 * v8::internal::Assembler::kInstrSize)); | 1115 __ ld(at, MemOperand(at, 4 * v8::internal::Assembler::kInstrSize)); |
1109 __ jr(at); | 1116 __ jr(at); |
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1408 } | 1415 } |
1409 } | 1416 } |
1410 MarkLazyDeoptSite(); | 1417 MarkLazyDeoptSite(); |
1411 } | 1418 } |
1412 | 1419 |
1413 #undef __ | 1420 #undef __ |
1414 | 1421 |
1415 } // namespace compiler | 1422 } // namespace compiler |
1416 } // namespace internal | 1423 } // namespace internal |
1417 } // namespace v8 | 1424 } // namespace v8 |
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