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Side by Side Diff: src/mips/assembler-mips.h

Issue 1131783003: Embedded constant pools. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix debug-mode Arm issue. Created 5 years, 6 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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493 // The high 8 bits are set to zero. 493 // The high 8 bits are set to zero.
494 void label_at_put(Label* L, int at_offset); 494 void label_at_put(Label* L, int at_offset);
495 495
496 // Read/Modify the code target address in the branch/call instruction at pc. 496 // Read/Modify the code target address in the branch/call instruction at pc.
497 static Address target_address_at(Address pc); 497 static Address target_address_at(Address pc);
498 static void set_target_address_at(Address pc, 498 static void set_target_address_at(Address pc,
499 Address target, 499 Address target,
500 ICacheFlushMode icache_flush_mode = 500 ICacheFlushMode icache_flush_mode =
501 FLUSH_ICACHE_IF_NEEDED); 501 FLUSH_ICACHE_IF_NEEDED);
502 // On MIPS there is no Constant Pool so we skip that parameter. 502 // On MIPS there is no Constant Pool so we skip that parameter.
503 INLINE(static Address target_address_at(Address pc, 503 INLINE(static Address target_address_at(Address pc, Address constant_pool)) {
504 ConstantPoolArray* constant_pool)) {
505 return target_address_at(pc); 504 return target_address_at(pc);
506 } 505 }
507 INLINE(static void set_target_address_at(Address pc, 506 INLINE(static void set_target_address_at(
508 ConstantPoolArray* constant_pool, 507 Address pc, Address constant_pool, Address target,
509 Address target, 508 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED)) {
510 ICacheFlushMode icache_flush_mode =
511 FLUSH_ICACHE_IF_NEEDED)) {
512 set_target_address_at(pc, target, icache_flush_mode); 509 set_target_address_at(pc, target, icache_flush_mode);
513 } 510 }
514 INLINE(static Address target_address_at(Address pc, Code* code)) { 511 INLINE(static Address target_address_at(Address pc, Code* code)) {
515 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL; 512 Address constant_pool = code ? code->constant_pool() : NULL;
516 return target_address_at(pc, constant_pool); 513 return target_address_at(pc, constant_pool);
517 } 514 }
518 INLINE(static void set_target_address_at(Address pc, 515 INLINE(static void set_target_address_at(Address pc,
519 Code* code, 516 Code* code,
520 Address target, 517 Address target,
521 ICacheFlushMode icache_flush_mode = 518 ICacheFlushMode icache_flush_mode =
522 FLUSH_ICACHE_IF_NEEDED)) { 519 FLUSH_ICACHE_IF_NEEDED)) {
523 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL; 520 Address constant_pool = code ? code->constant_pool() : NULL;
524 set_target_address_at(pc, constant_pool, target, icache_flush_mode); 521 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
525 } 522 }
526 523
527 // Return the code target address at a call site from the return address 524 // Return the code target address at a call site from the return address
528 // of that call in the instruction stream. 525 // of that call in the instruction stream.
529 inline static Address target_address_from_return_address(Address pc); 526 inline static Address target_address_from_return_address(Address pc);
530 527
531 // Return the code target address of the patch debug break slot 528 // Return the code target address of the patch debug break slot
532 inline static Address break_address_from_return_address(Address pc); 529 inline static Address break_address_from_return_address(Address pc);
533 530
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1074 void RecordDeoptReason(const int reason, const SourcePosition position); 1071 void RecordDeoptReason(const int reason, const SourcePosition position);
1075 1072
1076 1073
1077 static int RelocateInternalReference(RelocInfo::Mode rmode, byte* pc, 1074 static int RelocateInternalReference(RelocInfo::Mode rmode, byte* pc,
1078 intptr_t pc_delta); 1075 intptr_t pc_delta);
1079 1076
1080 // Writes a single byte or word of data in the code stream. Used for 1077 // Writes a single byte or word of data in the code stream. Used for
1081 // inline tables, e.g., jump-tables. 1078 // inline tables, e.g., jump-tables.
1082 void db(uint8_t data); 1079 void db(uint8_t data);
1083 void dd(uint32_t data); 1080 void dd(uint32_t data);
1081 void dq(uint64_t data);
1082 void dp(uintptr_t data) { dd(data); }
1084 void dd(Label* label); 1083 void dd(Label* label);
1085 1084
1086 // Emits the address of the code stub's first instruction. 1085 // Emits the address of the code stub's first instruction.
1087 void emit_code_stub_address(Code* stub); 1086 void emit_code_stub_address(Code* stub);
1088 1087
1089 PositionsRecorder* positions_recorder() { return &positions_recorder_; } 1088 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1090 1089
1091 // Postpone the generation of the trampoline pool for the specified number of 1090 // Postpone the generation of the trampoline pool for the specified number of
1092 // instructions. 1091 // instructions.
1093 void BlockTrampolinePoolFor(int instructions); 1092 void BlockTrampolinePoolFor(int instructions);
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1158 static bool IsSw(Instr instr); 1157 static bool IsSw(Instr instr);
1159 static Instr SetSwOffset(Instr instr, int16_t offset); 1158 static Instr SetSwOffset(Instr instr, int16_t offset);
1160 static bool IsAddImmediate(Instr instr); 1159 static bool IsAddImmediate(Instr instr);
1161 static Instr SetAddImmediateOffset(Instr instr, int16_t offset); 1160 static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
1162 1161
1163 static bool IsAndImmediate(Instr instr); 1162 static bool IsAndImmediate(Instr instr);
1164 static bool IsEmittedConstant(Instr instr); 1163 static bool IsEmittedConstant(Instr instr);
1165 1164
1166 void CheckTrampolinePool(); 1165 void CheckTrampolinePool();
1167 1166
1168 // Allocate a constant pool of the correct size for the generated code. 1167 void PatchConstantPoolAccessInstruction(int pc_offset, int offset,
1169 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate); 1168 ConstantPoolEntry::Access access,
1170 1169 ConstantPoolEntry::Type type) {
1171 // Generate the constant pool for the generated code. 1170 // No embedded constant pool support.
1172 void PopulateConstantPool(ConstantPoolArray* constant_pool); 1171 UNREACHABLE();
1172 }
1173 1173
1174 protected: 1174 protected:
1175 // Relocation for a type-recording IC has the AST id added to it. This 1175 // Relocation for a type-recording IC has the AST id added to it. This
1176 // member variable is a way to pass the information from the call site to 1176 // member variable is a way to pass the information from the call site to
1177 // the relocation info. 1177 // the relocation info.
1178 TypeFeedbackId recorded_ast_id_; 1178 TypeFeedbackId recorded_ast_id_;
1179 1179
1180 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; } 1180 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; }
1181 1181
1182 // Decode branch instruction at pos and return branch target pos. 1182 // Decode branch instruction at pos and return branch target pos.
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1441 class EnsureSpace BASE_EMBEDDED { 1441 class EnsureSpace BASE_EMBEDDED {
1442 public: 1442 public:
1443 explicit EnsureSpace(Assembler* assembler) { 1443 explicit EnsureSpace(Assembler* assembler) {
1444 assembler->CheckBuffer(); 1444 assembler->CheckBuffer();
1445 } 1445 }
1446 }; 1446 };
1447 1447
1448 } } // namespace v8::internal 1448 } } // namespace v8::internal
1449 1449
1450 #endif // V8_ARM_ASSEMBLER_MIPS_H_ 1450 #endif // V8_ARM_ASSEMBLER_MIPS_H_
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