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Side by Side Diff: src/mips/assembler-mips.h

Issue 1131783003: Embedded constant pools. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 7 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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493 // The high 8 bits are set to zero. 493 // The high 8 bits are set to zero.
494 void label_at_put(Label* L, int at_offset); 494 void label_at_put(Label* L, int at_offset);
495 495
496 // Read/Modify the code target address in the branch/call instruction at pc. 496 // Read/Modify the code target address in the branch/call instruction at pc.
497 static Address target_address_at(Address pc); 497 static Address target_address_at(Address pc);
498 static void set_target_address_at(Address pc, 498 static void set_target_address_at(Address pc,
499 Address target, 499 Address target,
500 ICacheFlushMode icache_flush_mode = 500 ICacheFlushMode icache_flush_mode =
501 FLUSH_ICACHE_IF_NEEDED); 501 FLUSH_ICACHE_IF_NEEDED);
502 // On MIPS there is no Constant Pool so we skip that parameter. 502 // On MIPS there is no Constant Pool so we skip that parameter.
503 INLINE(static Address target_address_at(Address pc, 503 INLINE(static Address target_address_at(Address pc, Address constant_pool)) {
504 ConstantPoolArray* constant_pool)) {
505 return target_address_at(pc); 504 return target_address_at(pc);
506 } 505 }
507 INLINE(static void set_target_address_at(Address pc, 506 INLINE(static void set_target_address_at(
508 ConstantPoolArray* constant_pool, 507 Address pc, Address constant_pool, Address target,
509 Address target, 508 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED)) {
510 ICacheFlushMode icache_flush_mode =
511 FLUSH_ICACHE_IF_NEEDED)) {
512 set_target_address_at(pc, target, icache_flush_mode); 509 set_target_address_at(pc, target, icache_flush_mode);
513 } 510 }
514 INLINE(static Address target_address_at(Address pc, Code* code)) { 511 INLINE(static Address target_address_at(Address pc, Code* code)) {
515 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL; 512 Address constant_pool = code ? code->constant_pool() : NULL;
516 return target_address_at(pc, constant_pool); 513 return target_address_at(pc, constant_pool);
517 } 514 }
518 INLINE(static void set_target_address_at(Address pc, 515 INLINE(static void set_target_address_at(Address pc,
519 Code* code, 516 Code* code,
520 Address target, 517 Address target,
521 ICacheFlushMode icache_flush_mode = 518 ICacheFlushMode icache_flush_mode =
522 FLUSH_ICACHE_IF_NEEDED)) { 519 FLUSH_ICACHE_IF_NEEDED)) {
523 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL; 520 Address constant_pool = code ? code->constant_pool() : NULL;
524 set_target_address_at(pc, constant_pool, target, icache_flush_mode); 521 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
525 } 522 }
526 523
527 // Return the code target address at a call site from the return address 524 // Return the code target address at a call site from the return address
528 // of that call in the instruction stream. 525 // of that call in the instruction stream.
529 inline static Address target_address_from_return_address(Address pc); 526 inline static Address target_address_from_return_address(Address pc);
530 527
531 // Return the code target address of the patch debug break slot 528 // Return the code target address of the patch debug break slot
532 inline static Address break_address_from_return_address(Address pc); 529 inline static Address break_address_from_return_address(Address pc);
533 530
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1047 void RecordDeoptReason(const int reason, const SourcePosition position); 1044 void RecordDeoptReason(const int reason, const SourcePosition position);
1048 1045
1049 1046
1050 static int RelocateInternalReference(RelocInfo::Mode rmode, byte* pc, 1047 static int RelocateInternalReference(RelocInfo::Mode rmode, byte* pc,
1051 intptr_t pc_delta); 1048 intptr_t pc_delta);
1052 1049
1053 // Writes a single byte or word of data in the code stream. Used for 1050 // Writes a single byte or word of data in the code stream. Used for
1054 // inline tables, e.g., jump-tables. 1051 // inline tables, e.g., jump-tables.
1055 void db(uint8_t data); 1052 void db(uint8_t data);
1056 void dd(uint32_t data); 1053 void dd(uint32_t data);
1054 void dq(uint64_t data);
1055 void dp(uintptr_t data) { dd(data); }
1057 void dd(Label* label); 1056 void dd(Label* label);
1058 1057
1059 // Emits the address of the code stub's first instruction. 1058 // Emits the address of the code stub's first instruction.
1060 void emit_code_stub_address(Code* stub); 1059 void emit_code_stub_address(Code* stub);
1061 1060
1062 PositionsRecorder* positions_recorder() { return &positions_recorder_; } 1061 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1063 1062
1064 // Postpone the generation of the trampoline pool for the specified number of 1063 // Postpone the generation of the trampoline pool for the specified number of
1065 // instructions. 1064 // instructions.
1066 void BlockTrampolinePoolFor(int instructions); 1065 void BlockTrampolinePoolFor(int instructions);
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1131 static bool IsSw(Instr instr); 1130 static bool IsSw(Instr instr);
1132 static Instr SetSwOffset(Instr instr, int16_t offset); 1131 static Instr SetSwOffset(Instr instr, int16_t offset);
1133 static bool IsAddImmediate(Instr instr); 1132 static bool IsAddImmediate(Instr instr);
1134 static Instr SetAddImmediateOffset(Instr instr, int16_t offset); 1133 static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
1135 1134
1136 static bool IsAndImmediate(Instr instr); 1135 static bool IsAndImmediate(Instr instr);
1137 static bool IsEmittedConstant(Instr instr); 1136 static bool IsEmittedConstant(Instr instr);
1138 1137
1139 void CheckTrampolinePool(); 1138 void CheckTrampolinePool();
1140 1139
1141 // Allocate a constant pool of the correct size for the generated code. 1140 void SetConstantPoolOffset(int pos, int offset,
1142 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate); 1141 ConstantPoolEntry::Access access,
1143 1142 ConstantPoolEntry::Type type) {
1144 // Generate the constant pool for the generated code. 1143 // No embedded constant pool support.
1145 void PopulateConstantPool(ConstantPoolArray* constant_pool); 1144 UNREACHABLE();
1145 }
1146 1146
1147 protected: 1147 protected:
1148 // Relocation for a type-recording IC has the AST id added to it. This 1148 // Relocation for a type-recording IC has the AST id added to it. This
1149 // member variable is a way to pass the information from the call site to 1149 // member variable is a way to pass the information from the call site to
1150 // the relocation info. 1150 // the relocation info.
1151 TypeFeedbackId recorded_ast_id_; 1151 TypeFeedbackId recorded_ast_id_;
1152 1152
1153 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; } 1153 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; }
1154 1154
1155 // Decode branch instruction at pos and return branch target pos. 1155 // Decode branch instruction at pos and return branch target pos.
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1414 class EnsureSpace BASE_EMBEDDED { 1414 class EnsureSpace BASE_EMBEDDED {
1415 public: 1415 public:
1416 explicit EnsureSpace(Assembler* assembler) { 1416 explicit EnsureSpace(Assembler* assembler) {
1417 assembler->CheckBuffer(); 1417 assembler->CheckBuffer();
1418 } 1418 }
1419 }; 1419 };
1420 1420
1421 } } // namespace v8::internal 1421 } } // namespace v8::internal
1422 1422
1423 #endif // V8_ARM_ASSEMBLER_MIPS_H_ 1423 #endif // V8_ARM_ASSEMBLER_MIPS_H_
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