ARM64: Enable shorten-64-to-32 warning

test/cctest/test-fuzz-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are met:
 //
 //   * Redistributions of source code must retain the above copyright notice,
 //     this list of conditions and the following disclaimer.
 //   * Redistributions in binary form must reproduce the above copyright notice,
 //     this list of conditions and the following disclaimer in the documentation
 //     and/or other materials provided with the distribution.
 //   * Neither the name of ARM Limited nor the names of its contributors may be
@@ skipping 25 matching lines @@
   // 43 million = ~1% of the instruction space.
   static const int instruction_count = 43 * 1024 * 1024;
 
   uint16_t seed[3] = {1, 2, 3};
   seed48(seed);
 
   Decoder<DispatchingDecoderVisitor> decoder;
   Instruction buffer[kInstructionSize];
 
   for (int i = 0; i < instruction_count; i++) {
-    uint32_t instr = mrand48();
+    uint32_t instr = static_cast<uint32_t>(mrand48());
     buffer->SetInstructionBits(instr);
     decoder.Decode(buffer);
   }
 }
 
 
 TEST(FUZZ_disasm) {
   // Feed noise into the disassembler to check that it doesn't crash.
   // 9 million = ~0.2% of the instruction space.
   static const int instruction_count = 9 * 1024 * 1024;
 
   uint16_t seed[3] = {42, 43, 44};
   seed48(seed);
 
   Decoder<DispatchingDecoderVisitor> decoder;
   Disassembler disasm;
   Instruction buffer[kInstructionSize];
 
   decoder.AppendVisitor(&disasm);
   for (int i = 0; i < instruction_count; i++) {
-    uint32_t instr = mrand48();
+    uint32_t instr = static_cast<uint32_t>(mrand48());
     buffer->SetInstructionBits(instr);
     decoder.Decode(buffer);
   }
 }