ARM64: Enable shorten-64-to-32 warning

src/arm64/simulator-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdlib.h>
 #include <cmath>
 #include <cstdarg>
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_ARM64
@@ skipping 885 matching lines @@
     return value;
   }
 
   switch (shift_type) {
     case LSL:
       return value << amount;
     case LSR:
       return static_cast<unsignedT>(value) >> amount;
     case ASR:
       return value >> amount;
-    case ROR:
+    case ROR: {
+      unsignedT mask = (static_cast<unsignedT>(1) << amount) - 1;
       return (static_cast<unsignedT>(value) >> amount) |
-              ((value & ((1L << amount) - 1L)) <<
-                  (sizeof(unsignedT) * 8 - amount));
+             ((value & mask) << (sizeof(mask) * 8 - amount));
+    }
     default:
       UNIMPLEMENTED();
       return 0;
   }
 }
 
 
 template <typename T>
 T Simulator::ExtendValue(T value, Extend extend_type, unsigned left_shift) {
   const unsigned kSignExtendBShift = (sizeof(T) - 1) * 8;
@@ skipping 472 matching lines @@
 
 
 void Simulator::VisitAddSubShifted(Instruction* instr) {
   Shift shift_type = static_cast<Shift>(instr->ShiftDP());
   unsigned shift_amount = instr->ImmDPShift();
 
   if (instr->SixtyFourBits()) {
     int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount);
     AddSubHelper(instr, op2);
   } else {
-    int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount);
+    int32_t op2 = static_cast<int32_t>(
+        ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount));
     AddSubHelper(instr, op2);
   }
 }
 
 
 void Simulator::VisitAddSubImmediate(Instruction* instr) {
   int64_t op2 = instr->ImmAddSub() << ((instr->ShiftAddSub() == 1) ? 12 : 0);
   if (instr->SixtyFourBits()) {
     AddSubHelper<int64_t>(instr, op2);
   } else {
-    AddSubHelper<int32_t>(instr, op2);
+    AddSubHelper<int32_t>(instr, static_cast<int32_t>(op2));
   }
 }
 
 
 void Simulator::VisitAddSubExtended(Instruction* instr) {
   Extend ext = static_cast<Extend>(instr->ExtendMode());
   unsigned left_shift = instr->ImmExtendShift();
   if (instr->SixtyFourBits()) {
     int64_t op2 = ExtendValue(xreg(instr->Rm()), ext, left_shift);
     AddSubHelper(instr, op2);
@@ skipping 26 matching lines @@
     op2 = (instr->Mask(NOT) == NOT) ? ~op2 : op2;
     LogicalHelper<int32_t>(instr, op2);
   }
 }
 
 
 void Simulator::VisitLogicalImmediate(Instruction* instr) {
   if (instr->SixtyFourBits()) {
     LogicalHelper<int64_t>(instr, instr->ImmLogical());
   } else {
-    LogicalHelper<int32_t>(instr, instr->ImmLogical());
+    LogicalHelper<int32_t>(instr, static_cast<int32_t>(instr->ImmLogical()));
   }
 }
 
 
 template<typename T>
 void Simulator::LogicalHelper(Instruction* instr, T op2) {
   T op1 = reg<T>(instr->Rn());
   T result = 0;
   bool update_flags = false;
 
@@ skipping 401 matching lines @@
   MoveWideImmediateOp mov_op =
     static_cast<MoveWideImmediateOp>(instr->Mask(MoveWideImmediateMask));
   int64_t new_xn_val = 0;
 
   bool is_64_bits = instr->SixtyFourBits() == 1;
   // Shift is limited for W operations.
   DCHECK(is_64_bits || (instr->ShiftMoveWide() < 2));
 
   // Get the shifted immediate.
   int64_t shift = instr->ShiftMoveWide() * 16;
-  int64_t shifted_imm16 = instr->ImmMoveWide() << shift;
+  int64_t shifted_imm16 = static_cast<int64_t>(instr->ImmMoveWide()) << shift;
 
   // Compute the new value.
   switch (mov_op) {
     case MOVN_w:
     case MOVN_x: {
         new_xn_val = ~shifted_imm16;
         if (!is_64_bits) new_xn_val &= kWRegMask;
       break;
     }
     case MOVK_w:
@@ skipping 12 matching lines @@
     default:
       UNREACHABLE();
   }
 
   // Update the destination register.
   set_xreg(instr->Rd(), new_xn_val);
 }
 
 
 void Simulator::VisitConditionalSelect(Instruction* instr) {
+  uint64_t new_val = xreg(instr->Rn());
   if (ConditionFailed(static_cast<Condition>(instr->Condition()))) {
-    uint64_t new_val = xreg(instr->Rm());
+    new_val = xreg(instr->Rm());
     switch (instr->Mask(ConditionalSelectMask)) {
-      case CSEL_w: set_wreg(instr->Rd(), new_val); break;
-      case CSEL_x: set_xreg(instr->Rd(), new_val); break;
-      case CSINC_w: set_wreg(instr->Rd(), new_val + 1); break;
-      case CSINC_x: set_xreg(instr->Rd(), new_val + 1); break;
-      case CSINV_w: set_wreg(instr->Rd(), ~new_val); break;
-      case CSINV_x: set_xreg(instr->Rd(), ~new_val); break;
-      case CSNEG_w: set_wreg(instr->Rd(), -new_val); break;
-      case CSNEG_x: set_xreg(instr->Rd(), -new_val); break;
+      case CSEL_w:
+      case CSEL_x:
+        break;
+      case CSINC_w:
+      case CSINC_x:
+        new_val++;
+        break;
+      case CSINV_w:
+      case CSINV_x:
+        new_val = ~new_val;
+        break;
+      case CSNEG_w:
+      case CSNEG_x:
+        new_val = -new_val;
+        break;
       default: UNIMPLEMENTED();
     }
+  }
+  if (instr->SixtyFourBits()) {
+    set_xreg(instr->Rd(), new_val);
   } else {
-    if (instr->SixtyFourBits()) {
-      set_xreg(instr->Rd(), xreg(instr->Rn()));
-    } else {
-      set_wreg(instr->Rd(), wreg(instr->Rn()));
-    }
+    set_wreg(instr->Rd(), static_cast<uint32_t>(new_val));
   }
 }
 
 
 void Simulator::VisitDataProcessing1Source(Instruction* instr) {
   unsigned dst = instr->Rd();
   unsigned src = instr->Rn();
 
   switch (instr->Mask(DataProcessing1SourceMask)) {
-    case RBIT_w: set_wreg(dst, ReverseBits(wreg(src), kWRegSizeInBits)); break;
-    case RBIT_x: set_xreg(dst, ReverseBits(xreg(src), kXRegSizeInBits)); break;
-    case REV16_w: set_wreg(dst, ReverseBytes(wreg(src), Reverse16)); break;
-    case REV16_x: set_xreg(dst, ReverseBytes(xreg(src), Reverse16)); break;
-    case REV_w: set_wreg(dst, ReverseBytes(wreg(src), Reverse32)); break;
-    case REV32_x: set_xreg(dst, ReverseBytes(xreg(src), Reverse32)); break;
-    case REV_x: set_xreg(dst, ReverseBytes(xreg(src), Reverse64)); break;
+    case RBIT_w:
+      set_wreg(dst, ReverseBits(wreg(src)));
+      break;
+    case RBIT_x:
+      set_xreg(dst, ReverseBits(xreg(src)));
+      break;
+    case REV16_w:
+      set_wreg(dst, ReverseBytes(wreg(src), 1));
+      break;
+    case REV16_x:
+      set_xreg(dst, ReverseBytes(xreg(src), 1));
+      break;
+    case REV_w:
+      set_wreg(dst, ReverseBytes(wreg(src), 2));
+      break;
+    case REV32_x:
+      set_xreg(dst, ReverseBytes(xreg(src), 2));
+      break;
+    case REV_x:
+      set_xreg(dst, ReverseBytes(xreg(src), 3));
+      break;
     case CLZ_w: set_wreg(dst, CountLeadingZeros(wreg(src), kWRegSizeInBits));
                 break;
     case CLZ_x: set_xreg(dst, CountLeadingZeros(xreg(src), kXRegSizeInBits));
                 break;
     case CLS_w: {
       set_wreg(dst, CountLeadingSignBits(wreg(src), kWRegSizeInBits));
       break;
     }
     case CLS_x: {
       set_xreg(dst, CountLeadingSignBits(xreg(src), kXRegSizeInBits));
       break;
     }
     default: UNIMPLEMENTED();
   }
 }
 
 
-uint64_t Simulator::ReverseBits(uint64_t value, unsigned num_bits) {
-  DCHECK((num_bits == kWRegSizeInBits) || (num_bits == kXRegSizeInBits));
-  uint64_t result = 0;
-  for (unsigned i = 0; i < num_bits; i++) {
-    result = (result << 1) | (value & 1);
-    value >>= 1;
-  }
-  return result;
-}
-
-
-uint64_t Simulator::ReverseBytes(uint64_t value, ReverseByteMode mode) {
-  // Split the 64-bit value into an 8-bit array, where b[0] is the least
-  // significant byte, and b[7] is the most significant.
-  uint8_t bytes[8];
-  uint64_t mask = 0xff00000000000000UL;
-  for (int i = 7; i >= 0; i--) {
-    bytes[i] = (value & mask) >> (i * 8);
-    mask >>= 8;
-  }
-
-  // Permutation tables for REV instructions.
-  //  permute_table[Reverse16] is used by REV16_x, REV16_w
-  //  permute_table[Reverse32] is used by REV32_x, REV_w
-  //  permute_table[Reverse64] is used by REV_x
-  DCHECK((Reverse16 == 0) && (Reverse32 == 1) && (Reverse64 == 2));
-  static const uint8_t permute_table[3][8] = { {6, 7, 4, 5, 2, 3, 0, 1},
-                                               {4, 5, 6, 7, 0, 1, 2, 3},
-                                               {0, 1, 2, 3, 4, 5, 6, 7} };
-  uint64_t result = 0;
-  for (int i = 0; i < 8; i++) {
-    result <<= 8;
-    result |= bytes[permute_table[mode][i]];
-  }
-  return result;
-}
-
-
 template <typename T>
 void Simulator::DataProcessing2Source(Instruction* instr) {
   Shift shift_op = NO_SHIFT;
   T result = 0;
   switch (instr->Mask(DataProcessing2SourceMask)) {
     case SDIV_w:
     case SDIV_x: {
       T rn = reg<T>(instr->Rn());
       T rm = reg<T>(instr->Rm());
       if ((rn == std::numeric_limits<T>::min()) && (rm == -1)) {
@@ skipping 99 matching lines @@
     case SMULH_x:
       DCHECK(instr->Ra() == kZeroRegCode);
       result = MultiplyHighSigned(xreg(instr->Rn()), xreg(instr->Rm()));
       break;
     default: UNIMPLEMENTED();
   }
 
   if (instr->SixtyFourBits()) {
     set_xreg(instr->Rd(), result);
   } else {
-    set_wreg(instr->Rd(), result);
+    set_wreg(instr->Rd(), static_cast<int32_t>(result));
   }
 }
 
 
 template <typename T>
 void Simulator::BitfieldHelper(Instruction* instr) {
   typedef typename make_unsigned<T>::type unsignedT;
   T reg_size = sizeof(T) * 8;
   T R = instr->ImmR();
   T S = instr->ImmS();
   T diff = S - R;
   T mask;
   if (diff >= 0) {
     mask = diff < reg_size - 1 ? (static_cast<T>(1) << (diff + 1)) - 1
                                : static_cast<T>(-1);
   } else {
-    mask = ((1L << (S + 1)) - 1);
-    mask = (static_cast<uint64_t>(mask) >> R) | (mask << (reg_size - R));
+    uint64_t umask = ((1L << (S + 1)) - 1);
+    umask = (umask >> R) | (umask << (reg_size - R));
+    mask = static_cast<T>(umask);
     diff += reg_size;
   }
 
   // inzero indicates if the extracted bitfield is inserted into the
   // destination register value or in zero.
   // If extend is true, extend the sign of the extracted bitfield.
   bool inzero = false;
   bool extend = false;
   switch (instr->Mask(BitfieldMask)) {
     case BFM_x:
@@ skipping 403 matching lines @@
   //
   //                   mantissa = (mantissa >> shift) + halfbit(adjusted);
 
   static const int mantissa_offset = 0;
   static const int exponent_offset = mantissa_offset + mbits;
   static const int sign_offset = exponent_offset + ebits;
   STATIC_ASSERT(sign_offset == (sizeof(T) * kByteSize - 1));
 
   // Bail out early for zero inputs.
   if (mantissa == 0) {
-    return sign << sign_offset;
+    return static_cast<T>(sign << sign_offset);
   }
 
   // If all bits in the exponent are set, the value is infinite or NaN.
   // This is true for all binary IEEE-754 formats.
   static const int infinite_exponent = (1 << ebits) - 1;
   static const int max_normal_exponent = infinite_exponent - 1;
 
   // Apply the exponent bias to encode it for the result. Doing this early makes
   // it easy to detect values that will be infinite or subnormal.
   exponent += max_normal_exponent >> 1;
 
   if (exponent > max_normal_exponent) {
     // Overflow: The input is too large for the result type to represent. The
     // FPTieEven rounding mode handles overflows using infinities.
     exponent = infinite_exponent;
     mantissa = 0;
-    return (sign << sign_offset) |
-           (exponent << exponent_offset) |
-           (mantissa << mantissa_offset);
+    return static_cast<T>((sign << sign_offset) |
+                          (exponent << exponent_offset) |
+                          (mantissa << mantissa_offset));
   }
 
   // Calculate the shift required to move the top mantissa bit to the proper
   // place in the destination type.
   const int highest_significant_bit = 63 - CountLeadingZeros(mantissa, 64);
   int shift = highest_significant_bit - mbits;
 
   if (exponent <= 0) {
     // The output will be subnormal (before rounding).
 
     // For subnormal outputs, the shift must be adjusted by the exponent. The +1
     // is necessary because the exponent of a subnormal value (encoded as 0) is
     // the same as the exponent of the smallest normal value (encoded as 1).
     shift += -exponent + 1;
 
     // Handle inputs that would produce a zero output.
     //
     // Shifts higher than highest_significant_bit+1 will always produce a zero
     // result. A shift of exactly highest_significant_bit+1 might produce a
     // non-zero result after rounding.
     if (shift > (highest_significant_bit + 1)) {
       // The result will always be +/-0.0.
-      return sign << sign_offset;
+      return static_cast<T>(sign << sign_offset);
     }
 
     // Properly encode the exponent for a subnormal output.
     exponent = 0;
   } else {
     // Clear the topmost mantissa bit, since this is not encoded in IEEE-754
     // normal values.
     mantissa &= ~(1UL << highest_significant_bit);
   }
 
   if (shift > 0) {
     // We have to shift the mantissa to the right. Some precision is lost, so we
     // need to apply rounding.
     uint64_t onebit_mantissa = (mantissa >> (shift)) & 1;
     uint64_t halfbit_mantissa = (mantissa >> (shift-1)) & 1;
     uint64_t adjusted = mantissa - (halfbit_mantissa & ~onebit_mantissa);
     T halfbit_adjusted = (adjusted >> (shift-1)) & 1;
 
-    T result = (sign << sign_offset) |
-               (exponent << exponent_offset) |
-               ((mantissa >> shift) << mantissa_offset);
+    T result =
+        static_cast<T>((sign << sign_offset) | (exponent << exponent_offset) |
+                       ((mantissa >> shift) << mantissa_offset));
 
     // A very large mantissa can overflow during rounding. If this happens, the
     // exponent should be incremented and the mantissa set to 1.0 (encoded as
     // 0). Applying halfbit_adjusted after assembling the float has the nice
     // side-effect that this case is handled for free.
     //
     // This also handles cases where a very large finite value overflows to
     // infinity, or where a very large subnormal value overflows to become
     // normal.
     return result + halfbit_adjusted;
   } else {
     // We have to shift the mantissa to the left (or not at all). The input
     // mantissa is exactly representable in the output mantissa, so apply no
     // rounding correction.
-    return (sign << sign_offset) |
-           (exponent << exponent_offset) |
-           ((mantissa << -shift) << mantissa_offset);
+    return static_cast<T>((sign << sign_offset) |
+                          (exponent << exponent_offset) |
+                          ((mantissa << -shift) << mantissa_offset));
   }
 }
 
 
 // See FPRound for a description of this function.
 static inline double FPRoundToDouble(int64_t sign, int64_t exponent,
                                      uint64_t mantissa, FPRounding round_mode) {
   int64_t bits =
       FPRound<int64_t, kDoubleExponentBits, kDoubleMantissaBits>(sign,
                                                                  exponent,
@@ skipping 174 matching lines @@
       if (fpcr().DN()) return kFP32DefaultNaN;
 
       // Convert NaNs as the processor would:
       //  - The sign is propagated.
       //  - The payload (mantissa) is transferred as much as possible, except
       //    that the top bit is forced to '1', making the result a quiet NaN.
       uint64_t raw = double_to_rawbits(value);
 
       uint32_t sign = raw >> 63;
       uint32_t exponent = (1 << 8) - 1;
-      uint32_t payload = unsigned_bitextract_64(50, 52 - 23, raw);
+      uint32_t payload =
+          static_cast<uint32_t>(unsigned_bitextract_64(50, 52 - 23, raw));
       payload |= (1 << 22);   // Force a quiet NaN.
 
       return rawbits_to_float((sign << 31) | (exponent << 23) | payload);
     }
 
     case FP_ZERO:
     case FP_INFINITE: {
       // In a C++ cast, any value representable in the target type will be
       // unchanged. This is always the case for +/-0.0 and infinities.
       return static_cast<float>(value);
     }
 
     case FP_NORMAL:
     case FP_SUBNORMAL: {
       // Convert double-to-float as the processor would, assuming that FPCR.FZ
       // (flush-to-zero) is not set.
       uint64_t raw = double_to_rawbits(value);
       // Extract the IEEE-754 double components.
       uint32_t sign = raw >> 63;
       // Extract the exponent and remove the IEEE-754 encoding bias.
-      int32_t exponent = unsigned_bitextract_64(62, 52, raw) - 1023;
+      int32_t exponent =
+          static_cast<int32_t>(unsigned_bitextract_64(62, 52, raw)) - 1023;
       // Extract the mantissa and add the implicit '1' bit.
       uint64_t mantissa = unsigned_bitextract_64(51, 0, raw);
       if (std::fpclassify(value) == FP_NORMAL) {
         mantissa |= (1UL << 52);
       }
       return FPRoundToFloat(sign, exponent, mantissa, round_mode);
     }
   }
 
   UNREACHABLE();
@@ skipping 330 matching lines @@
         switch (instr->ImmSystemRegister()) {
           case NZCV: set_xreg(instr->Rt(), nzcv().RawValue()); break;
           case FPCR: set_xreg(instr->Rt(), fpcr().RawValue()); break;
           default: UNIMPLEMENTED();
         }
         break;
       }
       case MSR: {
         switch (instr->ImmSystemRegister()) {
           case NZCV:
-            nzcv().SetRawValue(xreg(instr->Rt()));
+            nzcv().SetRawValue(wreg(instr->Rt()));
             LogSystemRegister(NZCV);
             break;
           case FPCR:
-            fpcr().SetRawValue(xreg(instr->Rt()));
+            fpcr().SetRawValue(wreg(instr->Rt()));
             LogSystemRegister(FPCR);
             break;
           default: UNIMPLEMENTED();
         }
         break;
       }
     }
   } else if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
     DCHECK(instr->Mask(SystemHintMask) == HINT);
     switch (instr->ImmHint()) {
@@ skipping 603 matching lines @@
 
   delete[] format;
 }
 
 
 #endif  // USE_SIMULATOR
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64