ARM64: Enable shorten-64-to-32 warning

src/arm64/macro-assembler-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_ARM64
 
 #include "src/base/bits.h"
 #include "src/base/division-by-constant.h"
@@ skipping 908 matching lines @@
 
 
 void MacroAssembler::PushPopQueue::PushQueued(
     PreambleDirective preamble_directive) {
   if (queued_.empty()) return;
 
   if (preamble_directive == WITH_PREAMBLE) {
     masm_->PushPreamble(size_);
   }
 
-  int count = queued_.size();
-  int index = 0;
+  size_t count = queued_.size();
+  size_t index = 0;
   while (index < count) {
     // PushHelper can only handle registers with the same size and type, and it
     // can handle only four at a time. Batch them up accordingly.
     CPURegister batch[4] = {NoReg, NoReg, NoReg, NoReg};
     int batch_index = 0;
     do {
       batch[batch_index++] = queued_[index++];
     } while ((batch_index < 4) && (index < count) &&
              batch[0].IsSameSizeAndType(queued_[index]));
 
     masm_->PushHelper(batch_index, batch[0].SizeInBytes(),
                       batch[0], batch[1], batch[2], batch[3]);
   }
 
   queued_.clear();
 }
 
 
 void MacroAssembler::PushPopQueue::PopQueued() {
   if (queued_.empty()) return;
 
-  int count = queued_.size();
-  int index = 0;
+  size_t count = queued_.size();
+  size_t index = 0;
   while (index < count) {
     // PopHelper can only handle registers with the same size and type, and it
     // can handle only four at a time. Batch them up accordingly.
     CPURegister batch[4] = {NoReg, NoReg, NoReg, NoReg};
     int batch_index = 0;
     do {
       batch[batch_index++] = queued_[index++];
     } while ((batch_index < 4) && (index < count) &&
              batch[0].IsSameSizeAndType(queued_[index]));
 
@@ skipping 292 matching lines @@
 
 
 void MacroAssembler::PushCalleeSavedRegisters() {
   // Ensure that the macro-assembler doesn't use any scratch registers.
   InstructionAccurateScope scope(this);
 
   // This method must not be called unless the current stack pointer is the
   // system stack pointer (csp).
   DCHECK(csp.Is(StackPointer()));
 
-  MemOperand tos(csp, -2 * kXRegSize, PreIndex);
+  MemOperand tos(csp, -2 * static_cast<int>(kXRegSize), PreIndex);
 
   stp(d14, d15, tos);
   stp(d12, d13, tos);
   stp(d10, d11, tos);
   stp(d8, d9, tos);
 
   stp(x29, x30, tos);
   stp(x27, x28, tos);    // x28 = jssp
   stp(x25, x26, tos);
   stp(x23, x24, tos);
@@ skipping 3409 matching lines @@
     Register map_in_out,
     Register scratch1,
     Register scratch2,
     Label* no_map_match) {
   // Load the global or builtins object from the current context.
   Ldr(scratch1, GlobalObjectMemOperand());
   Ldr(scratch1, FieldMemOperand(scratch1, GlobalObject::kNativeContextOffset));
 
   // Check that the function's map is the same as the expected cached map.
   Ldr(scratch1, ContextMemOperand(scratch1, Context::JS_ARRAY_MAPS_INDEX));
-  size_t offset = (expected_kind * kPointerSize) + FixedArrayBase::kHeaderSize;
+  int offset = (expected_kind * kPointerSize) + FixedArrayBase::kHeaderSize;
   Ldr(scratch2, FieldMemOperand(scratch1, offset));
   Cmp(map_in_out, scratch2);
   B(ne, no_map_match);
 
   // Use the transitioned cached map.
   offset = (transitioned_kind * kPointerSize) + FixedArrayBase::kHeaderSize;
   Ldr(map_in_out, FieldMemOperand(scratch1, offset));
 }
 
 
@@ skipping 401 matching lines @@
                               const Label* smi_check) {
   Assembler::BlockPoolsScope scope(masm);
   if (reg.IsValid()) {
     DCHECK(smi_check->is_bound());
     DCHECK(reg.Is64Bits());
 
     // Encode the register (x0-x30) in the lowest 5 bits, then the offset to
     // 'check' in the other bits. The possible offset is limited in that we
     // use BitField to pack the data, and the underlying data type is a
     // uint32_t.
-    uint32_t delta = __ InstructionsGeneratedSince(smi_check);
+    uint32_t delta =
+        static_cast<uint32_t>(__ InstructionsGeneratedSince(smi_check));
     __ InlineData(RegisterBits::encode(reg.code()) | DeltaBits::encode(delta));
   } else {
     DCHECK(!smi_check->is_bound());
 
     // An offset of 0 indicates that there is no patch site.
     __ InlineData(0);
   }
 }
 
 
 InlineSmiCheckInfo::InlineSmiCheckInfo(Address info)
     : reg_(NoReg), smi_check_(NULL) {
   InstructionSequence* inline_data = InstructionSequence::At(info);
   DCHECK(inline_data->IsInlineData());
   if (inline_data->IsInlineData()) {
     uint64_t payload = inline_data->InlineData();
     // We use BitField to decode the payload, and BitField can only handle
     // 32-bit values.
     DCHECK(is_uint32(payload));
     if (payload != 0) {
-      int reg_code = RegisterBits::decode(payload);
+      uint32_t payload32 = static_cast<uint32_t>(payload);
+      int reg_code = RegisterBits::decode(payload32);
       reg_ = Register::XRegFromCode(reg_code);
-      uint64_t smi_check_delta = DeltaBits::decode(payload);
+      int smi_check_delta = DeltaBits::decode(payload32);
       DCHECK(smi_check_delta != 0);
       smi_check_ = inline_data->preceding(smi_check_delta);
     }
   }
 }
 
 
 #undef __
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64