ARM64: Enable shorten-64-to-32 warning

src/arm64/instructions-arm64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM64_INSTRUCTIONS_ARM64_H_
 #define V8_ARM64_INSTRUCTIONS_ARM64_H_
 
 #include "src/arm64/constants-arm64.h"
 #include "src/arm64/utils-arm64.h"
 #include "src/globals.h"
@@ skipping 119 matching lines @@
   }
 
   V8_INLINE const Instruction* preceding(int count = 1) const {
     return following(-count);
   }
 
   V8_INLINE Instruction* preceding(int count = 1) {
     return following(-count);
   }
 
-  #define DEFINE_GETTER(Name, HighBit, LowBit, Func)             \
-  int64_t Name() const { return Func(HighBit, LowBit); }
+#define DEFINE_GETTER(Name, HighBit, LowBit, Func) \
+  int32_t Name() const { return Func(HighBit, LowBit); }
   INSTRUCTION_FIELDS_LIST(DEFINE_GETTER)
   #undef DEFINE_GETTER
 
   // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST),
   // formed from ImmPCRelLo and ImmPCRelHi.
   int ImmPCRel() const {
     DCHECK(IsPCRelAddressing());
-    int const offset = ((ImmPCRelHi() << ImmPCRelLo_width) | ImmPCRelLo());
-    int const width = ImmPCRelLo_width + ImmPCRelHi_width;
+    int offset = ((ImmPCRelHi() << ImmPCRelLo_width) | ImmPCRelLo());
+    int width = ImmPCRelLo_width + ImmPCRelHi_width;
     return signed_bitextract_32(width - 1, 0, offset);
   }
 
   uint64_t ImmLogical();
   float ImmFP32();
   double ImmFP64();
 
   LSDataSize SizeLSPair() const {
     return CalcLSPairDataSize(
         static_cast<LoadStorePairOp>(Mask(LoadStorePairMask)));
@@ skipping 201 matching lines @@
 
   // Find the PC offset encoded in this instruction. 'this' may be a branch or
   // a PC-relative addressing instruction.
   // The offset returned is unscaled.
   int64_t ImmPCOffset();
 
   // Find the target of this instruction. 'this' may be a branch or a
   // PC-relative addressing instruction.
   Instruction* ImmPCOffsetTarget();
 
-  static bool IsValidImmPCOffset(ImmBranchType branch_type, int32_t offset);
+  static bool IsValidImmPCOffset(ImmBranchType branch_type, ptrdiff_t offset);
   bool IsTargetInImmPCOffsetRange(Instruction* target);
   // Patch a PC-relative offset to refer to 'target'. 'this' may be a branch or
   // a PC-relative addressing instruction.
   void SetImmPCOffsetTarget(Instruction* target);
   void SetUnresolvedInternalReferenceImmTarget(Instruction* target);
   // Patch a literal load instruction to load from 'source'.
   void SetImmLLiteral(Instruction* source);
 
   uintptr_t LiteralAddress() {
     int offset = ImmLLiteral() << kLoadLiteralScaleLog2;
@@ skipping 19 matching lines @@
   template<typename T> V8_INLINE static Instruction* Cast(T src) {
     return reinterpret_cast<Instruction*>(src);
   }
 
   V8_INLINE ptrdiff_t DistanceTo(Instruction* target) {
     return reinterpret_cast<Address>(target) - reinterpret_cast<Address>(this);
   }
 
 
   static const int ImmPCRelRangeBitwidth = 21;
-  static bool IsValidPCRelOffset(int offset) {
-    return is_int21(offset);
-  }
+  static bool IsValidPCRelOffset(ptrdiff_t offset) { return is_int21(offset); }
   void SetPCRelImmTarget(Instruction* target);
   void SetBranchImmTarget(Instruction* target);
 };
 
 
 // Where Instruction looks at instructions generated by the Assembler,
 // InstructionSequence looks at instructions sequences generated by the
 // MacroAssembler.
 class InstructionSequence : public Instruction {
  public:
@@ skipping 106 matching lines @@
   TRACE_ENABLE   = 1 << 6,
   TRACE_DISABLE  = 2 << 6,
   TRACE_OVERRIDE = 3 << 6
 };
 
 
 } }  // namespace v8::internal
 
 
 #endif  // V8_ARM64_INSTRUCTIONS_ARM64_H_