ARM64: Enable shorten-64-to-32 warning

src/arm64/instructions-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_ARM64
 
 #define ARM64_DEFINE_FP_STATICS
 
@@ skipping 75 matching lines @@
   }
   return result;
 }
 
 
 // Logical immediates can't encode zero, so a return value of zero is used to
 // indicate a failure case. Specifically, where the constraints on imm_s are not
 // met.
 uint64_t Instruction::ImmLogical() {
   unsigned reg_size = SixtyFourBits() ? kXRegSizeInBits : kWRegSizeInBits;
-  int64_t n = BitN();
-  int64_t imm_s = ImmSetBits();
-  int64_t imm_r = ImmRotate();
+  int32_t n = BitN();
+  int32_t imm_s = ImmSetBits();
+  int32_t imm_r = ImmRotate();
 
   // An integer is constructed from the n, imm_s and imm_r bits according to
   // the following table:
   //
   //  N   imms    immr    size        S             R
   //  1  ssssss  rrrrrr    64    UInt(ssssss)  UInt(rrrrrr)
   //  0  0sssss  xrrrrr    32    UInt(sssss)   UInt(rrrrr)
   //  0  10ssss  xxrrrr    16    UInt(ssss)    UInt(rrrr)
   //  0  110sss  xxxrrr     8    UInt(sss)     UInt(rrr)
   //  0  1110ss  xxxxrr     4    UInt(ss)      UInt(rr)
@@ skipping 95 matching lines @@
   return offset;
 }
 
 
 Instruction* Instruction::ImmPCOffsetTarget() {
   return InstructionAtOffset(ImmPCOffset());
 }
 
 
 bool Instruction::IsValidImmPCOffset(ImmBranchType branch_type,
-                                     int32_t offset) {
+                                     ptrdiff_t offset) {
   return is_intn(offset, ImmBranchRangeBitwidth(branch_type));
 }
 
 
 bool Instruction::IsTargetInImmPCOffsetRange(Instruction* target) {
   return IsValidImmPCOffset(BranchType(), DistanceTo(target));
 }
 
 
 void Instruction::SetImmPCOffsetTarget(Instruction* target) {
@@ skipping 10 matching lines @@
 }
 
 
 void Instruction::SetPCRelImmTarget(Instruction* target) {
   // ADRP is not supported, so 'this' must point to an ADR instruction.
   DCHECK(IsAdr());
 
   ptrdiff_t target_offset = DistanceTo(target);
   Instr imm;
   if (Instruction::IsValidPCRelOffset(target_offset)) {
-    imm = Assembler::ImmPCRelAddress(target_offset);
+    imm = Assembler::ImmPCRelAddress(static_cast<int>(target_offset));
     SetInstructionBits(Mask(~ImmPCRel_mask) | imm);
   } else {
     PatchingAssembler patcher(this,
                               PatchingAssembler::kAdrFarPatchableNInstrs);
     patcher.PatchAdrFar(target_offset);
   }
 }
 
 
 void Instruction::SetBranchImmTarget(Instruction* target) {
   DCHECK(IsAligned(DistanceTo(target), kInstructionSize));
+  DCHECK(IsValidImmPCOffset(BranchType(),
+                            DistanceTo(target) >> kInstructionSizeLog2));
+  int offset = static_cast<int>(DistanceTo(target) >> kInstructionSizeLog2);
   Instr branch_imm = 0;
   uint32_t imm_mask = 0;
-  ptrdiff_t offset = DistanceTo(target) >> kInstructionSizeLog2;
   switch (BranchType()) {
     case CondBranchType: {
       branch_imm = Assembler::ImmCondBranch(offset);
       imm_mask = ImmCondBranch_mask;
       break;
     }
     case UncondBranchType: {
       branch_imm = Assembler::ImmUncondBranch(offset);
       imm_mask = ImmUncondBranch_mask;
       break;
@@ skipping 10 matching lines @@
     }
     default: UNREACHABLE();
   }
   SetInstructionBits(Mask(~imm_mask) | branch_imm);
 }
 
 
 void Instruction::SetUnresolvedInternalReferenceImmTarget(Instruction* target) {
   DCHECK(IsUnresolvedInternalReference());
   DCHECK(IsAligned(DistanceTo(target), kInstructionSize));
-
-  ptrdiff_t target_offset = DistanceTo(target) >> kInstructionSizeLog2;
-  DCHECK(is_int32(target_offset));
+  DCHECK(is_int32(DistanceTo(target) >> kInstructionSizeLog2));
+  int32_t target_offset =
+      static_cast<int32_t>(DistanceTo(target) >> kInstructionSizeLog2);
   uint32_t high16 = unsigned_bitextract_32(31, 16, target_offset);
   uint32_t low16 = unsigned_bitextract_32(15, 0, target_offset);
 
   PatchingAssembler patcher(this, 2);
   patcher.brk(high16);
   patcher.brk(low16);
 }
 
 
 void Instruction::SetImmLLiteral(Instruction* source) {
   DCHECK(IsLdrLiteral());
   DCHECK(IsAligned(DistanceTo(source), kInstructionSize));
-  ptrdiff_t offset = DistanceTo(source) >> kLoadLiteralScaleLog2;
-  Instr imm = Assembler::ImmLLiteral(offset);
+  DCHECK(Assembler::IsImmLLiteral(DistanceTo(source)));
+  Instr imm = Assembler::ImmLLiteral(
+      static_cast<int>(DistanceTo(source) >> kLoadLiteralScaleLog2));
   Instr mask = ImmLLiteral_mask;
 
   SetInstructionBits(Mask(~mask) | imm);
 }
 
 
 // TODO(jbramley): We can't put this inline in the class because things like
 // xzr and Register are not defined in that header. Consider adding
 // instructions-arm64-inl.h to work around this.
 bool InstructionSequence::IsInlineData() const {
@@ skipping 13 matching lines @@
   uint64_t payload = ImmMoveWide();
   // TODO(all): If we extend ::InlineData() to support bigger data, we need
   // to update this method too.
   return payload;
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64