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Side by Side Diff: src/arm64/assembler-arm64-inl.h

Issue 1131573006: ARM64: Enable shorten-64-to-32 warning (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 7 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_ARM64_ASSEMBLER_ARM64_INL_H_ 5 #ifndef V8_ARM64_ASSEMBLER_ARM64_INL_H_
6 #define V8_ARM64_ASSEMBLER_ARM64_INL_H_ 6 #define V8_ARM64_ASSEMBLER_ARM64_INL_H_
7 7
8 #include "src/arm64/assembler-arm64.h" 8 #include "src/arm64/assembler-arm64.h"
9 #include "src/assembler.h" 9 #include "src/assembler.h"
10 #include "src/debug.h" 10 #include "src/debug.h"
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1077 b40 &= ImmTestBranchBit40_mask; 1077 b40 &= ImmTestBranchBit40_mask;
1078 return b5 | b40; 1078 return b5 | b40;
1079 } 1079 }
1080 1080
1081 1081
1082 Instr Assembler::SF(Register rd) { 1082 Instr Assembler::SF(Register rd) {
1083 return rd.Is64Bits() ? SixtyFourBits : ThirtyTwoBits; 1083 return rd.Is64Bits() ? SixtyFourBits : ThirtyTwoBits;
1084 } 1084 }
1085 1085
1086 1086
1087 Instr Assembler::ImmAddSub(int64_t imm) { 1087 Instr Assembler::ImmAddSub(int imm) {
1088 DCHECK(IsImmAddSub(imm)); 1088 DCHECK(IsImmAddSub(imm));
1089 if (is_uint12(imm)) { // No shift required. 1089 if (is_uint12(imm)) { // No shift required.
1090 return imm << ImmAddSub_offset; 1090 imm <<= ImmAddSub_offset;
1091 } else { 1091 } else {
1092 return ((imm >> 12) << ImmAddSub_offset) | (1 << ShiftAddSub_offset); 1092 imm = ((imm >> 12) << ImmAddSub_offset) | (1 << ShiftAddSub_offset);
1093 } 1093 }
1094 return imm;
1094 } 1095 }
1095 1096
1096 1097
1097 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) { 1098 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
1098 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) || 1099 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
1099 ((reg_size == kWRegSizeInBits) && is_uint5(imms))); 1100 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
1100 USE(reg_size); 1101 USE(reg_size);
1101 return imms << ImmS_offset; 1102 return imms << ImmS_offset;
1102 } 1103 }
1103 1104
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1232 return imm2 << ImmBarrierType_offset; 1233 return imm2 << ImmBarrierType_offset;
1233 } 1234 }
1234 1235
1235 1236
1236 LSDataSize Assembler::CalcLSDataSize(LoadStoreOp op) { 1237 LSDataSize Assembler::CalcLSDataSize(LoadStoreOp op) {
1237 DCHECK((SizeLS_offset + SizeLS_width) == (kInstructionSize * 8)); 1238 DCHECK((SizeLS_offset + SizeLS_width) == (kInstructionSize * 8));
1238 return static_cast<LSDataSize>(op >> SizeLS_offset); 1239 return static_cast<LSDataSize>(op >> SizeLS_offset);
1239 } 1240 }
1240 1241
1241 1242
1242 Instr Assembler::ImmMoveWide(uint64_t imm) { 1243 Instr Assembler::ImmMoveWide(int imm) {
1243 DCHECK(is_uint16(imm)); 1244 DCHECK(is_uint16(imm));
1244 return imm << ImmMoveWide_offset; 1245 return imm << ImmMoveWide_offset;
1245 } 1246 }
1246 1247
1247 1248
1248 Instr Assembler::ShiftMoveWide(int64_t shift) { 1249 Instr Assembler::ShiftMoveWide(int shift) {
1249 DCHECK(is_uint2(shift)); 1250 DCHECK(is_uint2(shift));
1250 return shift << ShiftMoveWide_offset; 1251 return shift << ShiftMoveWide_offset;
1251 } 1252 }
1252 1253
1253 1254
1254 Instr Assembler::FPType(FPRegister fd) { 1255 Instr Assembler::FPType(FPRegister fd) {
1255 return fd.Is64Bits() ? FP64 : FP32; 1256 return fd.Is64Bits() ? FP64 : FP32;
1256 } 1257 }
1257 1258
1258 1259
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1293 1294
1294 1295
1295 void Assembler::ClearRecordedAstId() { 1296 void Assembler::ClearRecordedAstId() {
1296 recorded_ast_id_ = TypeFeedbackId::None(); 1297 recorded_ast_id_ = TypeFeedbackId::None();
1297 } 1298 }
1298 1299
1299 1300
1300 } } // namespace v8::internal 1301 } } // namespace v8::internal
1301 1302
1302 #endif // V8_ARM64_ASSEMBLER_ARM64_INL_H_ 1303 #endif // V8_ARM64_ASSEMBLER_ARM64_INL_H_
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