[turbofan] Make an OptionalOperator for MachineOperatorBuilder.

src/compiler/common-operator-reducer.cc

Index: src/compiler/common-operator-reducer.cc
diff --git a/src/compiler/common-operator-reducer.cc b/src/compiler/common-operator-reducer.cc
index 4bab1204787d1414c518112afbdab0c0c13c1073..14bf812243ce20fbb212d75a8cfd75ce26dc1fcb 100644
--- a/src/compiler/common-operator-reducer.cc
+++ b/src/compiler/common-operator-reducer.cc
@@ -179,15 +179,15 @@ Reduction CommonOperatorReducer::ReducePhi(Node* node) {
           }
         }
         if (mcond.left().Equals(vtrue) && mcond.right().Equals(vfalse) &&
-            machine()->HasFloat32Min()) {
+            machine()->Float32Min().IsSupported()) {
           // We might now be able to further reduce the {merge} node.
           Revisit(merge);
-          return Change(node, machine()->Float32Min(), vtrue, vfalse);
+          return Change(node, machine()->Float32Min().op(), vtrue, vfalse);
         } else if (mcond.left().Equals(vfalse) && mcond.right().Equals(vtrue) &&
-                   machine()->HasFloat32Max()) {
+                   machine()->Float32Max().IsSupported()) {
           // We might now be able to further reduce the {merge} node.
           Revisit(merge);
-          return Change(node, machine()->Float32Max(), vtrue, vfalse);
+          return Change(node, machine()->Float32Max().op(), vtrue, vfalse);
         }
       } else if (cond->opcode() == IrOpcode::kFloat64LessThan) {
         Float64BinopMatcher mcond(cond);
@@ -201,15 +201,15 @@ Reduction CommonOperatorReducer::ReducePhi(Node* node) {
           }
         }
         if (mcond.left().Equals(vtrue) && mcond.right().Equals(vfalse) &&
-            machine()->HasFloat64Min()) {
+            machine()->Float64Min().IsSupported()) {
           // We might now be able to further reduce the {merge} node.
           Revisit(merge);
-          return Change(node, machine()->Float64Min(), vtrue, vfalse);
+          return Change(node, machine()->Float64Min().op(), vtrue, vfalse);
         } else if (mcond.left().Equals(vfalse) && mcond.right().Equals(vtrue) &&
-                   machine()->HasFloat64Max()) {
+                   machine()->Float64Max().IsSupported()) {
           // We might now be able to further reduce the {merge} node.
           Revisit(merge);
-          return Change(node, machine()->Float64Max(), vtrue, vfalse);
+          return Change(node, machine()->Float64Max().op(), vtrue, vfalse);
         }
       }
     }
@@ -256,11 +256,11 @@ Reduction CommonOperatorReducer::ReduceSelect(Node* node) {
         }
       }
       if (mcond.left().Equals(vtrue) && mcond.right().Equals(vfalse) &&
-          machine()->HasFloat32Min()) {
-        return Change(node, machine()->Float32Min(), vtrue, vfalse);
+          machine()->Float32Min().IsSupported()) {
+        return Change(node, machine()->Float32Min().op(), vtrue, vfalse);
       } else if (mcond.left().Equals(vfalse) && mcond.right().Equals(vtrue) &&
-                 machine()->HasFloat32Max()) {
-        return Change(node, machine()->Float32Max(), vtrue, vfalse);
+                 machine()->Float32Max().IsSupported()) {
+        return Change(node, machine()->Float32Max().op(), vtrue, vfalse);
       }
       break;
     }
@@ -274,11 +274,11 @@ Reduction CommonOperatorReducer::ReduceSelect(Node* node) {
         }
       }
       if (mcond.left().Equals(vtrue) && mcond.right().Equals(vfalse) &&
-          machine()->HasFloat64Min()) {
-        return Change(node, machine()->Float64Min(), vtrue, vfalse);
+          machine()->Float64Min().IsSupported()) {
+        return Change(node, machine()->Float64Min().op(), vtrue, vfalse);
       } else if (mcond.left().Equals(vfalse) && mcond.right().Equals(vtrue) &&
-                 machine()->HasFloat64Max()) {
-        return Change(node, machine()->Float64Max(), vtrue, vfalse);
+                 machine()->Float64Max().IsSupported()) {
+        return Change(node, machine()->Float64Max().op(), vtrue, vfalse);
       }
       break;
     }