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| 1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2010 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 273 inline int SField() const { return Bit(20); } | 273 inline int SField() const { return Bit(20); } |
| 274 // with register | 274 // with register |
| 275 inline int RmField() const { return Bits(3, 0); } | 275 inline int RmField() const { return Bits(3, 0); } |
| 276 inline Shift ShiftField() const { return static_cast<Shift>(Bits(6, 5)); } | 276 inline Shift ShiftField() const { return static_cast<Shift>(Bits(6, 5)); } |
| 277 inline int RegShiftField() const { return Bit(4); } | 277 inline int RegShiftField() const { return Bit(4); } |
| 278 inline int RsField() const { return Bits(11, 8); } | 278 inline int RsField() const { return Bits(11, 8); } |
| 279 inline int ShiftAmountField() const { return Bits(11, 7); } | 279 inline int ShiftAmountField() const { return Bits(11, 7); } |
| 280 // with immediate | 280 // with immediate |
| 281 inline int RotateField() const { return Bits(11, 8); } | 281 inline int RotateField() const { return Bits(11, 8); } |
| 282 inline int Immed8Field() const { return Bits(7, 0); } | 282 inline int Immed8Field() const { return Bits(7, 0); } |
| 283 inline int Immed4Field() const { return Bits(19, 16); } |
| 284 inline int ImmedMovwMovtField() const { |
| 285 return Immed4Field() << 12 | Offset12Field(); } |
| 283 | 286 |
| 284 // Fields used in Load/Store instructions | 287 // Fields used in Load/Store instructions |
| 285 inline int PUField() const { return Bits(24, 23); } | 288 inline int PUField() const { return Bits(24, 23); } |
| 286 inline int BField() const { return Bit(22); } | 289 inline int BField() const { return Bit(22); } |
| 287 inline int WField() const { return Bit(21); } | 290 inline int WField() const { return Bit(21); } |
| 288 inline int LField() const { return Bit(20); } | 291 inline int LField() const { return Bit(20); } |
| 289 // with register uses same fields as Data processing instructions above | 292 // with register uses same fields as Data processing instructions above |
| 290 // with immediate | 293 // with immediate |
| 291 inline int Offset12Field() const { return Bits(11, 0); } | 294 inline int Offset12Field() const { return Bits(11, 0); } |
| 292 // multiple | 295 // multiple |
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| 363 static int Number(const char* name, bool* is_double); | 366 static int Number(const char* name, bool* is_double); |
| 364 | 367 |
| 365 private: | 368 private: |
| 366 static const char* names_[kNumVFPRegisters]; | 369 static const char* names_[kNumVFPRegisters]; |
| 367 }; | 370 }; |
| 368 | 371 |
| 369 | 372 |
| 370 } } // namespace assembler::arm | 373 } } // namespace assembler::arm |
| 371 | 374 |
| 372 #endif // V8_ARM_CONSTANTS_ARM_H_ | 375 #endif // V8_ARM_CONSTANTS_ARM_H_ |
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