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Issue 11280080: MIPS: Lattice-based representation inference, powered by left/right specific type feedback for Bina… (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 8 years, 1 month ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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1688 return le; 1688 return le;
1689 case Token::GTE: 1689 case Token::GTE:
1690 return ge; 1690 return ge;
1691 default: 1691 default:
1692 UNREACHABLE(); 1692 UNREACHABLE();
1693 return kNoCondition; 1693 return kNoCondition;
1694 } 1694 }
1695 } 1695 }
1696 1696
1697 1697
1698 void CompareIC::UpdateCaches(Handle<Object> x, Handle<Object> y) { 1698 bool CompareIC::HasInlinedSmiCode(Address address) {
1699 HandleScope scope; 1699 // The address of the instruction following the call.
1700 Handle<Code> rewritten; 1700 Address andi_instruction_address =
1701 State previous_state = GetState(); 1701 address + Assembler::kCallTargetAddressOffset;
1702 State state = TargetState(previous_state, false, x, y);
1703 if (state == GENERIC) {
1704 CompareStub stub(GetCondition(), strict(), NO_COMPARE_FLAGS, a1, a0);
1705 rewritten = stub.GetCode();
1706 } else {
1707 ICCompareStub stub(op_, state);
1708 if (state == KNOWN_OBJECTS) {
1709 stub.set_known_map(Handle<Map>(Handle<JSObject>::cast(x)->map()));
1710 }
1711 rewritten = stub.GetCode();
1712 }
1713 set_target(*rewritten);
1714 1702
1715 #ifdef DEBUG 1703 // If the instruction following the call is not a andi at, rx, #yyy, nothing
1716 if (FLAG_trace_ic) { 1704 // was inlined.
1717 PrintF("[CompareIC (%s->%s)#%s]\n", 1705 Instr instr = Assembler::instr_at(andi_instruction_address);
1718 GetStateName(previous_state), 1706 return Assembler::IsAndImmediate(instr) &&
1719 GetStateName(state), 1707 Assembler::GetRt(instr) == (uint32_t)zero_reg.code();
1720 Token::Name(op_));
1721 }
1722 #endif
1723
1724 // Activate inlined smi code.
1725 if (previous_state == UNINITIALIZED) {
1726 PatchInlinedSmiCode(address(), ENABLE_INLINED_SMI_CHECK);
1727 }
1728 } 1708 }
1729 1709
1730 1710
1731 void PatchInlinedSmiCode(Address address, InlinedSmiCheck check) { 1711 void PatchInlinedSmiCode(Address address, InlinedSmiCheck check) {
1732 Address andi_instruction_address = 1712 Address andi_instruction_address =
1733 address + Assembler::kCallTargetAddressOffset; 1713 address + Assembler::kCallTargetAddressOffset;
1734 1714
1735 // If the instruction following the call is not a andi at, rx, #yyy, nothing 1715 // If the instruction following the call is not a andi at, rx, #yyy, nothing
1736 // was inlined. 1716 // was inlined.
1737 Instr instr = Assembler::instr_at(andi_instruction_address); 1717 Instr instr = Assembler::instr_at(andi_instruction_address);
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1787 } else { 1767 } else {
1788 ASSERT(Assembler::IsBne(branch_instr)); 1768 ASSERT(Assembler::IsBne(branch_instr));
1789 patcher.ChangeBranchCondition(eq); 1769 patcher.ChangeBranchCondition(eq);
1790 } 1770 }
1791 } 1771 }
1792 1772
1793 1773
1794 } } // namespace v8::internal 1774 } } // namespace v8::internal
1795 1775
1796 #endif // V8_TARGET_ARCH_MIPS 1776 #endif // V8_TARGET_ARCH_MIPS
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