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| 1 // Copyright 2011-2012 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are |
| 4 // met: |
| 5 // |
| 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided |
| 11 // with the distribution. |
| 12 // * Neither the name of Google Inc. nor the names of its |
| 13 // contributors may be used to endorse or promote products derived |
| 14 // from this software without specific prior written permission. |
| 15 // |
| 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 |
| 28 #include "v8.h" |
| 29 |
| 30 #if defined(V8_TARGET_ARCH_SH4) |
| 31 |
| 32 #include "macro-assembler.h" |
| 33 |
| 34 #include "checks-sh4.h" |
| 35 |
| 36 |
| 37 namespace v8 { |
| 38 namespace internal { |
| 39 |
| 40 inline void asm_output(const char *str, int a = 0 , int b = 0, int c = 0) {} |
| 41 #define REGNUM(reg) (reg).code() |
| 42 |
| 43 void Assembler::add_imm_(int imm, Register Rd) { |
| 44 ASSERT(REGNUM(Rd) <= 15 && SH4_CHECK_RANGE_add_imm(imm)); |
| 45 emit((0x7 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((imm & 0xFF) << 0)); |
| 46 asm_output("add_imm %d, R%d", imm, REGNUM(Rd)); |
| 47 } |
| 48 |
| 49 |
| 50 void Assembler::add_(Register Rs, Register Rd) { |
| 51 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 52 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 53 (0xC << 0)); |
| 54 asm_output("add R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 55 } |
| 56 |
| 57 |
| 58 void Assembler::addc_(Register Rs, Register Rd) { |
| 59 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 60 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 61 (0xE << 0)); |
| 62 asm_output("addc R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 63 } |
| 64 |
| 65 |
| 66 void Assembler::addv_(Register Rs, Register Rd) { |
| 67 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 68 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 69 (0xF << 0)); |
| 70 asm_output("addv R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 71 } |
| 72 |
| 73 |
| 74 void Assembler::and_imm_R0_(int imm) { |
| 75 ASSERT(SH4_CHECK_RANGE_and_imm_R0(imm)); |
| 76 emit((0xC << 12) | (0x9 << 8) | ((imm & 0xFF) << 0)); |
| 77 asm_output("and_imm_R0 %d", imm); |
| 78 } |
| 79 |
| 80 |
| 81 void Assembler::and_(Register Rs, Register Rd) { |
| 82 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 83 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 84 (0x9 << 0)); |
| 85 asm_output("and R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 86 } |
| 87 |
| 88 |
| 89 void Assembler::andb_imm_dispR0GBR_(int imm) { |
| 90 ASSERT(SH4_CHECK_RANGE_andb_imm_dispR0GBR(imm)); |
| 91 emit((0xC << 12) | (0xD << 8) | ((imm & 0xFF) << 0)); |
| 92 asm_output("andb_imm_dispR0GBR %d", imm); |
| 93 } |
| 94 |
| 95 |
| 96 void Assembler::bra_(int imm) { |
| 97 ASSERT(SH4_CHECK_RANGE_bra(imm) && SH4_CHECK_ALIGN_bra(imm)); |
| 98 emit((0xA << 12) | (((imm & 0x1FFE) >> 1) << 0)); |
| 99 asm_output("bra %d", imm); |
| 100 } |
| 101 |
| 102 |
| 103 void Assembler::bsr_(int imm) { |
| 104 ASSERT(SH4_CHECK_RANGE_bsr(imm) && SH4_CHECK_ALIGN_bsr(imm)); |
| 105 emit((0xB << 12) | (((imm & 0x1FFE) >> 1) << 0)); |
| 106 asm_output("bsr %d", imm); |
| 107 } |
| 108 |
| 109 |
| 110 void Assembler::bt_(int imm) { |
| 111 ASSERT(SH4_CHECK_RANGE_bt(imm) && SH4_CHECK_ALIGN_bt(imm)); |
| 112 emit((0x8 << 12) | (0x9 << 8) | (((imm & 0x1FE) >> 1) << 0)); |
| 113 asm_output("bt %d", imm); |
| 114 } |
| 115 |
| 116 |
| 117 void Assembler::bf_(int imm) { |
| 118 ASSERT(SH4_CHECK_RANGE_bf(imm) && SH4_CHECK_ALIGN_bf(imm)); |
| 119 emit((0x8 << 12) | (0xB << 8) | (((imm & 0x1FE) >> 1) << 0)); |
| 120 asm_output("bf %d", imm); |
| 121 } |
| 122 |
| 123 |
| 124 void Assembler::bts_(int imm) { |
| 125 ASSERT(SH4_CHECK_RANGE_bts(imm) && SH4_CHECK_ALIGN_bts(imm)); |
| 126 emit((0x8 << 12) | (0xD << 8) | (((imm & 0x1FE) >> 1) << 0)); |
| 127 asm_output("bts %d", imm); |
| 128 } |
| 129 |
| 130 |
| 131 void Assembler::bfs_(int imm) { |
| 132 ASSERT(SH4_CHECK_RANGE_bfs(imm) && SH4_CHECK_ALIGN_bfs(imm)); |
| 133 emit((0x8 << 12) | (0xF << 8) | (((imm & 0x1FE) >> 1) << 0)); |
| 134 asm_output("bfs %d", imm); |
| 135 } |
| 136 |
| 137 |
| 138 void Assembler::clrmac_() { |
| 139 emit((0x0 << 12) | (0x0 << 8) | (0x2 << 4) | (0x8 << 0)); |
| 140 asm_output("clrmac"); |
| 141 } |
| 142 |
| 143 |
| 144 void Assembler::clrs_() { |
| 145 emit((0x0 << 12) | (0x0 << 8) | (0x4 << 4) | (0x8 << 0)); |
| 146 asm_output("clrs"); |
| 147 } |
| 148 |
| 149 |
| 150 void Assembler::clrt_() { |
| 151 emit((0x0 << 12) | (0x0 << 8) | (0x0 << 4) | (0x8 << 0)); |
| 152 asm_output("clrt"); |
| 153 } |
| 154 |
| 155 |
| 156 void Assembler::cmpeq_imm_R0_(int imm) { |
| 157 ASSERT(SH4_CHECK_RANGE_cmpeq_imm_R0(imm)); |
| 158 emit((0x8 << 12) | (0x8 << 8) | ((imm & 0xFF) << 0)); |
| 159 asm_output("cmpeq_imm_R0 %d", imm); |
| 160 } |
| 161 |
| 162 |
| 163 void Assembler::cmpeq_(Register Rs, Register Rd) { |
| 164 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 165 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 166 (0x0 << 0)); |
| 167 asm_output("cmpeq R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 168 } |
| 169 |
| 170 |
| 171 void Assembler::cmpge_(Register Rs, Register Rd) { |
| 172 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 173 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 174 (0x3 << 0)); |
| 175 asm_output("cmpge R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 176 } |
| 177 |
| 178 |
| 179 void Assembler::cmpgt_(Register Rs, Register Rd) { |
| 180 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 181 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 182 (0x7 << 0)); |
| 183 asm_output("cmpgt R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 184 } |
| 185 |
| 186 |
| 187 void Assembler::cmphi_(Register Rs, Register Rd) { |
| 188 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 189 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 190 (0x6 << 0)); |
| 191 asm_output("cmphi R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 192 } |
| 193 |
| 194 |
| 195 void Assembler::cmphs_(Register Rs, Register Rd) { |
| 196 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 197 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 198 (0x2 << 0)); |
| 199 asm_output("cmphs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 200 } |
| 201 |
| 202 |
| 203 void Assembler::cmppl_(Register Rd) { |
| 204 ASSERT(REGNUM(Rd) <= 15); |
| 205 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0x5 << 0)); |
| 206 asm_output("cmppl R%d", REGNUM(Rd)); |
| 207 } |
| 208 |
| 209 |
| 210 void Assembler::cmppz_(Register Rd) { |
| 211 ASSERT(REGNUM(Rd) <= 15); |
| 212 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0x1 << 0)); |
| 213 asm_output("cmppz R%d", REGNUM(Rd)); |
| 214 } |
| 215 |
| 216 |
| 217 void Assembler::cmpstr_(Register Rs, Register Rd) { |
| 218 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 219 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 220 (0xC << 0)); |
| 221 asm_output("cmpstr R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 222 } |
| 223 |
| 224 |
| 225 void Assembler::div0s_(Register Rs, Register Rd) { |
| 226 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 227 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 228 (0x7 << 0)); |
| 229 asm_output("div0s R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 230 } |
| 231 |
| 232 |
| 233 void Assembler::div0u_() { |
| 234 emit((0x0 << 12) | (0x0 << 8) | (0x1 << 4) | (0x9 << 0)); |
| 235 asm_output("div0u"); |
| 236 } |
| 237 |
| 238 |
| 239 void Assembler::div1_(Register Rs, Register Rd) { |
| 240 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 241 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 242 (0x4 << 0)); |
| 243 asm_output("div1 R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 244 } |
| 245 |
| 246 |
| 247 void Assembler::extsb_(Register Rs, Register Rd) { |
| 248 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 249 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 250 (0xE << 0)); |
| 251 asm_output("extsb R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 252 } |
| 253 |
| 254 |
| 255 void Assembler::extsw_(Register Rs, Register Rd) { |
| 256 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 257 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 258 (0xF << 0)); |
| 259 asm_output("extsw R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 260 } |
| 261 |
| 262 |
| 263 void Assembler::extub_(Register Rs, Register Rd) { |
| 264 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 265 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 266 (0xC << 0)); |
| 267 asm_output("extub R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 268 } |
| 269 |
| 270 |
| 271 void Assembler::extuw_(Register Rs, Register Rd) { |
| 272 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 273 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 274 (0xD << 0)); |
| 275 asm_output("extuw R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 276 } |
| 277 |
| 278 |
| 279 void Assembler::icbi_indRd_(Register Rd) { |
| 280 ASSERT(REGNUM(Rd) <= 15); |
| 281 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xE << 4) | (0x3 << 0)); |
| 282 asm_output("icbi_indRd R%d", REGNUM(Rd)); |
| 283 } |
| 284 |
| 285 |
| 286 void Assembler::jmp_indRd_(Register Rd) { |
| 287 ASSERT(REGNUM(Rd) <= 15); |
| 288 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0xB << 0)); |
| 289 asm_output("jmp_indRd R%d", REGNUM(Rd)); |
| 290 } |
| 291 |
| 292 |
| 293 void Assembler::jsr_indRd_(Register Rd) { |
| 294 ASSERT(REGNUM(Rd) <= 15); |
| 295 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0xB << 0)); |
| 296 asm_output("jsr_indRd R%d", REGNUM(Rd)); |
| 297 } |
| 298 |
| 299 |
| 300 void Assembler::ldc_SR_(Register Rd) { |
| 301 ASSERT(REGNUM(Rd) <= 15); |
| 302 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0xE << 0)); |
| 303 asm_output("ldc_SR R%d", REGNUM(Rd)); |
| 304 } |
| 305 |
| 306 |
| 307 void Assembler::ldc_GBR_(Register Rd) { |
| 308 ASSERT(REGNUM(Rd) <= 15); |
| 309 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0xE << 0)); |
| 310 asm_output("ldc_GBR R%d", REGNUM(Rd)); |
| 311 } |
| 312 |
| 313 |
| 314 void Assembler::ldc_SGR_(Register Rd) { |
| 315 ASSERT(REGNUM(Rd) <= 15); |
| 316 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x3 << 4) | (0xA << 0)); |
| 317 asm_output("ldc_SGR R%d", REGNUM(Rd)); |
| 318 } |
| 319 |
| 320 |
| 321 void Assembler::ldc_VBR_(Register Rd) { |
| 322 ASSERT(REGNUM(Rd) <= 15); |
| 323 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0xE << 0)); |
| 324 asm_output("ldc_VBR R%d", REGNUM(Rd)); |
| 325 } |
| 326 |
| 327 |
| 328 void Assembler::ldc_SSR_(Register Rd) { |
| 329 ASSERT(REGNUM(Rd) <= 15); |
| 330 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x3 << 4) | (0xE << 0)); |
| 331 asm_output("ldc_SSR R%d", REGNUM(Rd)); |
| 332 } |
| 333 |
| 334 |
| 335 void Assembler::ldc_SPC_(Register Rd) { |
| 336 ASSERT(REGNUM(Rd) <= 15); |
| 337 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x4 << 4) | (0xE << 0)); |
| 338 asm_output("ldc_SPC R%d", REGNUM(Rd)); |
| 339 } |
| 340 |
| 341 |
| 342 void Assembler::ldc_DBR_(Register Rd) { |
| 343 ASSERT(REGNUM(Rd) <= 15); |
| 344 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xF << 4) | (0xA << 0)); |
| 345 asm_output("ldc_DBR R%d", REGNUM(Rd)); |
| 346 } |
| 347 |
| 348 |
| 349 void Assembler::ldc_bank_(Register Rd, int imm) { |
| 350 ASSERT(REGNUM(Rd) <= 15 && SH4_CHECK_RANGE_ldc_bank(imm)); |
| 351 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((imm & 0x7) << 4) | |
| 352 (0xE << 0)); |
| 353 asm_output("ldc_bank R%d, %d", REGNUM(Rd), imm); |
| 354 } |
| 355 |
| 356 |
| 357 void Assembler::ldcl_incRd_SR_(Register Rd) { |
| 358 ASSERT(REGNUM(Rd) <= 15); |
| 359 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x7 << 0)); |
| 360 asm_output("ldcl_incRd_SR R%d", REGNUM(Rd)); |
| 361 } |
| 362 |
| 363 |
| 364 void Assembler::ldcl_incRd_GBR_(Register Rd) { |
| 365 ASSERT(REGNUM(Rd) <= 15); |
| 366 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0x7 << 0)); |
| 367 asm_output("ldcl_incRd_GBR R%d", REGNUM(Rd)); |
| 368 } |
| 369 |
| 370 |
| 371 void Assembler::ldcl_incRd_VBR_(Register Rd) { |
| 372 ASSERT(REGNUM(Rd) <= 15); |
| 373 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x7 << 0)); |
| 374 asm_output("ldcl_incRd_VBR R%d", REGNUM(Rd)); |
| 375 } |
| 376 |
| 377 |
| 378 void Assembler::ldcl_incRd_SGR_(Register Rd) { |
| 379 ASSERT(REGNUM(Rd) <= 15); |
| 380 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x3 << 4) | (0x6 << 0)); |
| 381 asm_output("ldcl_incRd_SGR R%d", REGNUM(Rd)); |
| 382 } |
| 383 |
| 384 |
| 385 void Assembler::ldcl_incRd_SSR_(Register Rd) { |
| 386 ASSERT(REGNUM(Rd) <= 15); |
| 387 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x3 << 4) | (0x7 << 0)); |
| 388 asm_output("ldcl_incRd_SSR R%d", REGNUM(Rd)); |
| 389 } |
| 390 |
| 391 |
| 392 void Assembler::ldcl_incRd_SPC_(Register Rd) { |
| 393 ASSERT(REGNUM(Rd) <= 15); |
| 394 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x4 << 4) | (0x7 << 0)); |
| 395 asm_output("ldcl_incRd_SPC R%d", REGNUM(Rd)); |
| 396 } |
| 397 |
| 398 |
| 399 void Assembler::ldcl_incRd_DBR_(Register Rd) { |
| 400 ASSERT(REGNUM(Rd) <= 15); |
| 401 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xF << 4) | (0x6 << 0)); |
| 402 asm_output("ldcl_incRd_DBR R%d", REGNUM(Rd)); |
| 403 } |
| 404 |
| 405 |
| 406 void Assembler::ldcl_incRd_bank_(Register Rd, int imm) { |
| 407 ASSERT(REGNUM(Rd) <= 15 && SH4_CHECK_RANGE_ldcl_incRd_bank(imm)); |
| 408 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((imm & 0x7) << 4) | |
| 409 (0x7 << 0)); |
| 410 asm_output("ldcl_incRd_bank R%d, %d", REGNUM(Rd), imm); |
| 411 } |
| 412 |
| 413 |
| 414 void Assembler::lds_MACH_(Register Rd) { |
| 415 ASSERT(REGNUM(Rd) <= 15); |
| 416 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0xA << 0)); |
| 417 asm_output("lds_MACH R%d", REGNUM(Rd)); |
| 418 } |
| 419 |
| 420 |
| 421 void Assembler::lds_MACL_(Register Rd) { |
| 422 ASSERT(REGNUM(Rd) <= 15); |
| 423 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0xA << 0)); |
| 424 asm_output("lds_MACL R%d", REGNUM(Rd)); |
| 425 } |
| 426 |
| 427 |
| 428 void Assembler::lds_PR_(Register Rd) { |
| 429 ASSERT(REGNUM(Rd) <= 15); |
| 430 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0xA << 0)); |
| 431 asm_output("lds_PR R%d", REGNUM(Rd)); |
| 432 } |
| 433 |
| 434 |
| 435 void Assembler::lds_FPUL_(Register Rs) { |
| 436 ASSERT(REGNUM(Rs) <= 15); |
| 437 emit((0x4 << 12) | ((REGNUM(Rs) & 0xF) << 8) | (0x5 << 4) | (0xA << 0)); |
| 438 asm_output("lds_FPUL R%d", REGNUM(Rs)); |
| 439 } |
| 440 |
| 441 |
| 442 void Assembler::lds_FPSCR_(Register Rs) { |
| 443 ASSERT(REGNUM(Rs) <= 15); |
| 444 emit((0x4 << 12) | ((REGNUM(Rs) & 0xF) << 8) | (0x6 << 4) | (0xA << 0)); |
| 445 asm_output("lds_FPSCR R%d", REGNUM(Rs)); |
| 446 } |
| 447 |
| 448 |
| 449 void Assembler::ldsl_incRd_MACH_(Register Rd) { |
| 450 ASSERT(REGNUM(Rd) <= 15); |
| 451 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x6 << 0)); |
| 452 asm_output("ldsl_incRd_MACH R%d", REGNUM(Rd)); |
| 453 } |
| 454 |
| 455 |
| 456 void Assembler::ldsl_incRd_MACL_(Register Rd) { |
| 457 ASSERT(REGNUM(Rd) <= 15); |
| 458 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0x6 << 0)); |
| 459 asm_output("ldsl_incRd_MACL R%d", REGNUM(Rd)); |
| 460 } |
| 461 |
| 462 |
| 463 void Assembler::ldsl_incRd_PR_(Register Rd) { |
| 464 ASSERT(REGNUM(Rd) <= 15); |
| 465 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x6 << 0)); |
| 466 asm_output("ldsl_incRd_PR R%d", REGNUM(Rd)); |
| 467 } |
| 468 |
| 469 |
| 470 void Assembler::ldsl_incRs_FPUL_(Register Rs) { |
| 471 ASSERT(REGNUM(Rs) <= 15); |
| 472 emit((0x4 << 12) | ((REGNUM(Rs) & 0xF) << 8) | (0x5 << 4) | (0x6 << 0)); |
| 473 asm_output("ldsl_incRs_FPUL R%d", REGNUM(Rs)); |
| 474 } |
| 475 |
| 476 |
| 477 void Assembler::ldsl_incRs_FPSCR_(Register Rs) { |
| 478 ASSERT(REGNUM(Rs) <= 15); |
| 479 emit((0x4 << 12) | ((REGNUM(Rs) & 0xF) << 8) | (0x6 << 4) | (0x6 << 0)); |
| 480 asm_output("ldsl_incRs_FPSCR R%d", REGNUM(Rs)); |
| 481 } |
| 482 |
| 483 |
| 484 void Assembler::ldtlb_() { |
| 485 emit((0x0 << 12) | (0x0 << 8) | (0x3 << 4) | (0x8 << 0)); |
| 486 asm_output("ldtlb"); |
| 487 } |
| 488 |
| 489 |
| 490 void Assembler::macw_incRs_incRd_(Register Rs, Register Rd) { |
| 491 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 492 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 493 (0xF << 0)); |
| 494 asm_output("macw_incRs_incRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 495 } |
| 496 |
| 497 |
| 498 void Assembler::mov_imm_(int imm, Register Rd) { |
| 499 ASSERT(REGNUM(Rd) <= 15 && SH4_CHECK_RANGE_mov_imm(imm)); |
| 500 emit((0xE << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((imm & 0xFF) << 0)); |
| 501 asm_output("mov_imm %d, R%d", imm, REGNUM(Rd)); |
| 502 } |
| 503 |
| 504 |
| 505 void Assembler::mov_(Register Rs, Register Rd) { |
| 506 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 507 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 508 (0x3 << 0)); |
| 509 asm_output("mov R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 510 } |
| 511 |
| 512 |
| 513 void Assembler::movb_dispR0Rd_(Register Rs, Register Rd) { |
| 514 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 515 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 516 (0x4 << 0)); |
| 517 asm_output("movb_dispR0Rd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 518 } |
| 519 |
| 520 |
| 521 void Assembler::movb_decRd_(Register Rs, Register Rd) { |
| 522 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 523 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 524 (0x4 << 0)); |
| 525 asm_output("movb_decRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 526 } |
| 527 |
| 528 |
| 529 void Assembler::movb_indRd_(Register Rs, Register Rd) { |
| 530 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 531 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 532 (0x0 << 0)); |
| 533 asm_output("movb_indRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 534 } |
| 535 |
| 536 |
| 537 void Assembler::movb_dispRs_R0_(int imm, Register Rs) { |
| 538 ASSERT(REGNUM(Rs) <= 15 && SH4_CHECK_RANGE_movb_dispRs_R0(imm)); |
| 539 emit((0x8 << 12) | (0x4 << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 540 ((imm & 0xF) << 0)); |
| 541 asm_output("movb_dispRs_R0 %d, R%d", imm, REGNUM(Rs)); |
| 542 } |
| 543 |
| 544 |
| 545 void Assembler::movb_dispGBR_R0_(int imm) { |
| 546 ASSERT(SH4_CHECK_RANGE_movb_dispGBR_R0(imm)); |
| 547 emit((0xC << 12) | (0x4 << 8) | ((imm & 0xFF) << 0)); |
| 548 asm_output("movb_dispGBR_R0 %d", imm); |
| 549 } |
| 550 |
| 551 |
| 552 void Assembler::movb_dispR0Rs_(Register Rs, Register Rd) { |
| 553 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 554 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 555 (0xC << 0)); |
| 556 asm_output("movb_dispR0Rs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 557 } |
| 558 |
| 559 |
| 560 void Assembler::movb_incRs_(Register Rs, Register Rd) { |
| 561 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 562 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 563 (0x4 << 0)); |
| 564 asm_output("movb_incRs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 565 } |
| 566 |
| 567 |
| 568 void Assembler::movb_indRs_(Register Rs, Register Rd) { |
| 569 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 570 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 571 (0x0 << 0)); |
| 572 asm_output("movb_indRs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 573 } |
| 574 |
| 575 |
| 576 void Assembler::movb_R0_dispRd_(int imm, Register Rd) { |
| 577 ASSERT(REGNUM(Rd) <= 15 && SH4_CHECK_RANGE_movb_R0_dispRd(imm)); |
| 578 emit((0x8 << 12) | (0x0 << 8) | ((REGNUM(Rd) & 0xF) << 4) | |
| 579 ((imm & 0xF) << 0)); |
| 580 asm_output("movb_R0_dispRd %d, R%d", imm, REGNUM(Rd)); |
| 581 } |
| 582 |
| 583 |
| 584 void Assembler::movb_R0_dispGBR_(int imm) { |
| 585 ASSERT(SH4_CHECK_RANGE_movb_R0_dispGBR(imm)); |
| 586 emit((0xC << 12) | (0x0 << 8) | ((imm & 0xFF) << 0)); |
| 587 asm_output("movb_R0_dispGBR %d", imm); |
| 588 } |
| 589 |
| 590 |
| 591 void Assembler::movl_dispRd_(Register Rs, int imm, Register Rd) { |
| 592 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15 && |
| 593 SH4_CHECK_RANGE_movl_dispRd(imm) && SH4_CHECK_ALIGN_movl_dispRd(imm)); |
| 594 emit((0x1 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 595 (((imm & 0x3C) >> 2) << 0)); |
| 596 asm_output("movl_dispRd R%d, %d, R%d", REGNUM(Rs), imm, REGNUM(Rd)); |
| 597 } |
| 598 |
| 599 |
| 600 void Assembler::movl_dispR0Rd_(Register Rs, Register Rd) { |
| 601 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 602 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 603 (0x6 << 0)); |
| 604 asm_output("movl_dispR0Rd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 605 } |
| 606 |
| 607 |
| 608 void Assembler::movl_decRd_(Register Rs, Register Rd) { |
| 609 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 610 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 611 (0x6 << 0)); |
| 612 asm_output("movl_decRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 613 } |
| 614 |
| 615 |
| 616 void Assembler::movl_indRd_(Register Rs, Register Rd) { |
| 617 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 618 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 619 (0x2 << 0)); |
| 620 asm_output("movl_indRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 621 } |
| 622 |
| 623 |
| 624 void Assembler::movl_dispRs_(int imm, Register Rs, Register Rd) { |
| 625 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15 && |
| 626 SH4_CHECK_RANGE_movl_dispRs(imm) && SH4_CHECK_ALIGN_movl_dispRs(imm)); |
| 627 emit((0x5 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 628 (((imm & 0x3C) >> 2) << 0)); |
| 629 asm_output("movl_dispRs %d, R%d, R%d", imm, REGNUM(Rs), REGNUM(Rd)); |
| 630 } |
| 631 |
| 632 |
| 633 void Assembler::movl_dispGBR_R0_(int imm) { |
| 634 ASSERT(SH4_CHECK_RANGE_movl_dispGBR_R0(imm) && |
| 635 SH4_CHECK_ALIGN_movl_dispGBR_R0(imm)); |
| 636 emit((0xC << 12) | (0x6 << 8) | (((imm & 0x3FC) >> 2) << 0)); |
| 637 asm_output("movl_dispGBR_R0 %d", imm); |
| 638 } |
| 639 |
| 640 |
| 641 void Assembler::movl_dispPC_(int imm, Register Rd) { |
| 642 ASSERT(REGNUM(Rd) <= 15 && SH4_CHECK_RANGE_movl_dispPC(imm) && |
| 643 SH4_CHECK_ALIGN_movl_dispPC(imm)); |
| 644 emit((0xD << 12) | ((REGNUM(Rd) & 0xF) << 8) | (((imm & 0x3FC) >> 2) << 0)); |
| 645 asm_output("movl_dispPC %d, R%d", imm, REGNUM(Rd)); |
| 646 } |
| 647 |
| 648 |
| 649 void Assembler::movl_dispR0Rs_(Register Rs, Register Rd) { |
| 650 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 651 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 652 (0xE << 0)); |
| 653 asm_output("movl_dispR0Rs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 654 } |
| 655 |
| 656 |
| 657 void Assembler::movl_incRs_(Register Rs, Register Rd) { |
| 658 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 659 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 660 (0x6 << 0)); |
| 661 asm_output("movl_incRs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 662 } |
| 663 |
| 664 |
| 665 void Assembler::movl_indRs_(Register Rs, Register Rd) { |
| 666 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 667 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 668 (0x2 << 0)); |
| 669 asm_output("movl_indRs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 670 } |
| 671 |
| 672 |
| 673 void Assembler::movl_R0_dispGBR_(int imm) { |
| 674 ASSERT(SH4_CHECK_RANGE_movl_R0_dispGBR(imm) && |
| 675 SH4_CHECK_ALIGN_movl_R0_dispGBR(imm)); |
| 676 emit((0xC << 12) | (0x2 << 8) | (((imm & 0x3FC) >> 2) << 0)); |
| 677 asm_output("movl_R0_dispGBR %d", imm); |
| 678 } |
| 679 |
| 680 |
| 681 void Assembler::movw_dispR0Rd_(Register Rs, Register Rd) { |
| 682 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 683 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 684 (0x5 << 0)); |
| 685 asm_output("movw_dispR0Rd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 686 } |
| 687 |
| 688 |
| 689 void Assembler::movw_decRd_(Register Rs, Register Rd) { |
| 690 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 691 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 692 (0x5 << 0)); |
| 693 asm_output("movw_decRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 694 } |
| 695 |
| 696 |
| 697 void Assembler::movw_indRd_(Register Rs, Register Rd) { |
| 698 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 699 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 700 (0x1 << 0)); |
| 701 asm_output("movw_indRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 702 } |
| 703 |
| 704 |
| 705 void Assembler::movw_dispRs_R0_(int imm, Register Rs) { |
| 706 ASSERT(REGNUM(Rs) <= 15 && SH4_CHECK_RANGE_movw_dispRs_R0(imm) && |
| 707 SH4_CHECK_ALIGN_movw_dispRs_R0(imm)); |
| 708 emit((0x8 << 12) | (0x5 << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 709 (((imm & 0x1E) >> 1) << 0)); |
| 710 asm_output("movw_dispRs_R0 %d, R%d", imm, REGNUM(Rs)); |
| 711 } |
| 712 |
| 713 |
| 714 void Assembler::movw_dispGBR_R0_(int imm) { |
| 715 ASSERT(SH4_CHECK_RANGE_movw_dispGBR_R0(imm) && |
| 716 SH4_CHECK_ALIGN_movw_dispGBR_R0(imm)); |
| 717 emit((0xC << 12) | (0x5 << 8) | (((imm & 0x1FE) >> 1) << 0)); |
| 718 asm_output("movw_dispGBR_R0 %d", imm); |
| 719 } |
| 720 |
| 721 |
| 722 void Assembler::movw_dispPC_(int imm, Register Rd) { |
| 723 ASSERT(REGNUM(Rd) <= 15 && SH4_CHECK_RANGE_movw_dispPC(imm) && |
| 724 SH4_CHECK_ALIGN_movw_dispPC(imm)); |
| 725 emit((0x9 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (((imm & 0x1FE) >> 1) << 0)); |
| 726 asm_output("movw_dispPC %d, R%d", imm, REGNUM(Rd)); |
| 727 } |
| 728 |
| 729 |
| 730 void Assembler::movw_dispR0Rs_(Register Rs, Register Rd) { |
| 731 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 732 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 733 (0xD << 0)); |
| 734 asm_output("movw_dispR0Rs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 735 } |
| 736 |
| 737 |
| 738 void Assembler::movw_incRs_(Register Rs, Register Rd) { |
| 739 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 740 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 741 (0x5 << 0)); |
| 742 asm_output("movw_incRs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 743 } |
| 744 |
| 745 |
| 746 void Assembler::movw_indRs_(Register Rs, Register Rd) { |
| 747 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 748 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 749 (0x1 << 0)); |
| 750 asm_output("movw_indRs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 751 } |
| 752 |
| 753 |
| 754 void Assembler::movw_R0_dispRd_(int imm, Register Rd) { |
| 755 ASSERT(REGNUM(Rd) <= 15 && SH4_CHECK_RANGE_movw_R0_dispRd(imm) && |
| 756 SH4_CHECK_ALIGN_movw_R0_dispRd(imm)); |
| 757 emit((0x8 << 12) | (0x1 << 8) | ((REGNUM(Rd) & 0xF) << 4) | |
| 758 (((imm & 0x1E) >> 1) << 0)); |
| 759 asm_output("movw_R0_dispRd %d, R%d", imm, REGNUM(Rd)); |
| 760 } |
| 761 |
| 762 |
| 763 void Assembler::movw_R0_dispGBR_(int imm) { |
| 764 ASSERT(SH4_CHECK_RANGE_movw_R0_dispGBR(imm) && |
| 765 SH4_CHECK_ALIGN_movw_R0_dispGBR(imm)); |
| 766 emit((0xC << 12) | (0x1 << 8) | (((imm & 0x1FE) >> 1) << 0)); |
| 767 asm_output("movw_R0_dispGBR %d", imm); |
| 768 } |
| 769 |
| 770 |
| 771 void Assembler::mova_dispPC_R0_(int imm) { |
| 772 ASSERT(SH4_CHECK_RANGE_mova_dispPC_R0(imm) && |
| 773 SH4_CHECK_ALIGN_mova_dispPC_R0(imm)); |
| 774 emit((0xC << 12) | (0x7 << 8) | (((imm & 0x3FC) >> 2) << 0)); |
| 775 asm_output("mova_dispPC_R0 %d", imm); |
| 776 } |
| 777 |
| 778 |
| 779 void Assembler::movcal_R0_indRd_(Register Rd) { |
| 780 ASSERT(REGNUM(Rd) <= 15); |
| 781 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xC << 4) | (0x3 << 0)); |
| 782 asm_output("movcal_R0_indRd R%d", REGNUM(Rd)); |
| 783 } |
| 784 |
| 785 |
| 786 void Assembler::movcol_R0_indRd_(Register Rd) { |
| 787 ASSERT(REGNUM(Rd) <= 15); |
| 788 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x7 << 4) | (0x3 << 0)); |
| 789 asm_output("movcol_R0_indRd R%d", REGNUM(Rd)); |
| 790 } |
| 791 |
| 792 |
| 793 void Assembler::movlil_indRs_R0_(Register Rs) { |
| 794 ASSERT(REGNUM(Rs) <= 15); |
| 795 emit((0x0 << 12) | ((REGNUM(Rs) & 0xF) << 8) | (0x6 << 4) | (0x3 << 0)); |
| 796 asm_output("movlil_indRs_R0 R%d", REGNUM(Rs)); |
| 797 } |
| 798 |
| 799 |
| 800 void Assembler::movt_(Register Rd) { |
| 801 ASSERT(REGNUM(Rd) <= 15); |
| 802 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x9 << 0)); |
| 803 asm_output("movt R%d", REGNUM(Rd)); |
| 804 } |
| 805 |
| 806 |
| 807 void Assembler::movual_indRs_R0_(Register Rs) { |
| 808 ASSERT(REGNUM(Rs) <= 15); |
| 809 emit((0x4 << 12) | ((REGNUM(Rs) & 0xF) << 8) | (0xA << 4) | (0x9 << 0)); |
| 810 asm_output("movual_indRs_R0 R%d", REGNUM(Rs)); |
| 811 } |
| 812 |
| 813 |
| 814 void Assembler::movual_incRs_R0_(Register Rs) { |
| 815 ASSERT(REGNUM(Rs) <= 15); |
| 816 emit((0x4 << 12) | ((REGNUM(Rs) & 0xF) << 8) | (0xE << 4) | (0x9 << 0)); |
| 817 asm_output("movual_incRs_R0 R%d", REGNUM(Rs)); |
| 818 } |
| 819 |
| 820 |
| 821 void Assembler::mulsw_(Register Rs, Register Rd) { |
| 822 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 823 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 824 (0xF << 0)); |
| 825 asm_output("mulsw R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 826 } |
| 827 |
| 828 |
| 829 void Assembler::muls_(Register Rs, Register Rd) { |
| 830 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 831 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 832 (0xF << 0)); |
| 833 asm_output("muls R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 834 } |
| 835 |
| 836 |
| 837 void Assembler::mull_(Register Rs, Register Rd) { |
| 838 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 839 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 840 (0x7 << 0)); |
| 841 asm_output("mull R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 842 } |
| 843 |
| 844 |
| 845 void Assembler::muluw_(Register Rs, Register Rd) { |
| 846 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 847 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 848 (0xE << 0)); |
| 849 asm_output("muluw R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 850 } |
| 851 |
| 852 |
| 853 void Assembler::mulu_(Register Rs, Register Rd) { |
| 854 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 855 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 856 (0xE << 0)); |
| 857 asm_output("mulu R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 858 } |
| 859 |
| 860 |
| 861 void Assembler::neg_(Register Rs, Register Rd) { |
| 862 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 863 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 864 (0xB << 0)); |
| 865 asm_output("neg R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 866 } |
| 867 |
| 868 |
| 869 void Assembler::negc_(Register Rs, Register Rd) { |
| 870 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 871 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 872 (0xA << 0)); |
| 873 asm_output("negc R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 874 } |
| 875 |
| 876 |
| 877 void Assembler::nop_() { |
| 878 emit((0x0 << 12) | (0x0 << 8) | (0x0 << 4) | (0x9 << 0)); |
| 879 asm_output("nop"); |
| 880 } |
| 881 |
| 882 |
| 883 void Assembler::not_(Register Rs, Register Rd) { |
| 884 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 885 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 886 (0x7 << 0)); |
| 887 asm_output("not R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 888 } |
| 889 |
| 890 |
| 891 void Assembler::ocbi_indRd_(Register Rd) { |
| 892 ASSERT(REGNUM(Rd) <= 15); |
| 893 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x9 << 4) | (0x3 << 0)); |
| 894 asm_output("ocbi_indRd R%d", REGNUM(Rd)); |
| 895 } |
| 896 |
| 897 |
| 898 void Assembler::ocbp_indRd_(Register Rd) { |
| 899 ASSERT(REGNUM(Rd) <= 15); |
| 900 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xA << 4) | (0x3 << 0)); |
| 901 asm_output("ocbp_indRd R%d", REGNUM(Rd)); |
| 902 } |
| 903 |
| 904 |
| 905 void Assembler::ocbwb_indRd_(Register Rd) { |
| 906 ASSERT(REGNUM(Rd) <= 15); |
| 907 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xB << 4) | (0x3 << 0)); |
| 908 asm_output("ocbwb_indRd R%d", REGNUM(Rd)); |
| 909 } |
| 910 |
| 911 |
| 912 void Assembler::or_imm_R0_(int imm) { |
| 913 ASSERT(SH4_CHECK_RANGE_or_imm_R0(imm)); |
| 914 emit((0xC << 12) | (0xB << 8) | ((imm & 0xFF) << 0)); |
| 915 asm_output("or_imm_R0 %d", imm); |
| 916 } |
| 917 |
| 918 |
| 919 void Assembler::or_(Register Rs, Register Rd) { |
| 920 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 921 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 922 (0xB << 0)); |
| 923 asm_output("or R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 924 } |
| 925 |
| 926 |
| 927 void Assembler::orb_imm_dispR0GBR_(int imm) { |
| 928 ASSERT(SH4_CHECK_RANGE_orb_imm_dispR0GBR(imm)); |
| 929 emit((0xC << 12) | (0xF << 8) | ((imm & 0xFF) << 0)); |
| 930 asm_output("orb_imm_dispR0GBR %d", imm); |
| 931 } |
| 932 |
| 933 |
| 934 void Assembler::pref_indRd_(Register Rd) { |
| 935 ASSERT(REGNUM(Rd) <= 15); |
| 936 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x8 << 4) | (0x3 << 0)); |
| 937 asm_output("pref_indRd R%d", REGNUM(Rd)); |
| 938 } |
| 939 |
| 940 |
| 941 void Assembler::prefi_indRd_(Register Rd) { |
| 942 ASSERT(REGNUM(Rd) <= 15); |
| 943 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xD << 4) | (0x3 << 0)); |
| 944 asm_output("prefi_indRd R%d", REGNUM(Rd)); |
| 945 } |
| 946 |
| 947 |
| 948 void Assembler::rotcl_(Register Rd) { |
| 949 ASSERT(REGNUM(Rd) <= 15); |
| 950 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x4 << 0)); |
| 951 asm_output("rotcl R%d", REGNUM(Rd)); |
| 952 } |
| 953 |
| 954 |
| 955 void Assembler::rotcr_(Register Rd) { |
| 956 ASSERT(REGNUM(Rd) <= 15); |
| 957 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x5 << 0)); |
| 958 asm_output("rotcr R%d", REGNUM(Rd)); |
| 959 } |
| 960 |
| 961 |
| 962 void Assembler::rotl_(Register Rd) { |
| 963 ASSERT(REGNUM(Rd) <= 15); |
| 964 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x4 << 0)); |
| 965 asm_output("rotl R%d", REGNUM(Rd)); |
| 966 } |
| 967 |
| 968 |
| 969 void Assembler::rotr_(Register Rd) { |
| 970 ASSERT(REGNUM(Rd) <= 15); |
| 971 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x5 << 0)); |
| 972 asm_output("rotr R%d", REGNUM(Rd)); |
| 973 } |
| 974 |
| 975 |
| 976 void Assembler::rte_() { |
| 977 emit((0x0 << 12) | (0x0 << 8) | (0x2 << 4) | (0xB << 0)); |
| 978 asm_output("rte"); |
| 979 } |
| 980 |
| 981 |
| 982 void Assembler::rts_() { |
| 983 emit((0x0 << 12) | (0x0 << 8) | (0x0 << 4) | (0xB << 0)); |
| 984 asm_output("rts"); |
| 985 } |
| 986 |
| 987 |
| 988 void Assembler::sets_() { |
| 989 emit((0x0 << 12) | (0x0 << 8) | (0x5 << 4) | (0x8 << 0)); |
| 990 asm_output("sets"); |
| 991 } |
| 992 |
| 993 |
| 994 void Assembler::sett_() { |
| 995 emit((0x0 << 12) | (0x0 << 8) | (0x1 << 4) | (0x8 << 0)); |
| 996 asm_output("sett"); |
| 997 } |
| 998 |
| 999 |
| 1000 void Assembler::shad_(Register Rs, Register Rd) { |
| 1001 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1002 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1003 (0xC << 0)); |
| 1004 asm_output("shad R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1005 } |
| 1006 |
| 1007 |
| 1008 void Assembler::shld_(Register Rs, Register Rd) { |
| 1009 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1010 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1011 (0xD << 0)); |
| 1012 asm_output("shld R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1013 } |
| 1014 |
| 1015 |
| 1016 void Assembler::shal_(Register Rd) { |
| 1017 ASSERT(REGNUM(Rd) <= 15); |
| 1018 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x0 << 0)); |
| 1019 asm_output("shal R%d", REGNUM(Rd)); |
| 1020 } |
| 1021 |
| 1022 |
| 1023 void Assembler::shar_(Register Rd) { |
| 1024 ASSERT(REGNUM(Rd) <= 15); |
| 1025 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x1 << 0)); |
| 1026 asm_output("shar R%d", REGNUM(Rd)); |
| 1027 } |
| 1028 |
| 1029 |
| 1030 void Assembler::shll_(Register Rd) { |
| 1031 ASSERT(REGNUM(Rd) <= 15); |
| 1032 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x0 << 0)); |
| 1033 asm_output("shll R%d", REGNUM(Rd)); |
| 1034 } |
| 1035 |
| 1036 |
| 1037 void Assembler::shll16_(Register Rd) { |
| 1038 ASSERT(REGNUM(Rd) <= 15); |
| 1039 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x8 << 0)); |
| 1040 asm_output("shll16 R%d", REGNUM(Rd)); |
| 1041 } |
| 1042 |
| 1043 |
| 1044 void Assembler::shll2_(Register Rd) { |
| 1045 ASSERT(REGNUM(Rd) <= 15); |
| 1046 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x8 << 0)); |
| 1047 asm_output("shll2 R%d", REGNUM(Rd)); |
| 1048 } |
| 1049 |
| 1050 |
| 1051 void Assembler::shll8_(Register Rd) { |
| 1052 ASSERT(REGNUM(Rd) <= 15); |
| 1053 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0x8 << 0)); |
| 1054 asm_output("shll8 R%d", REGNUM(Rd)); |
| 1055 } |
| 1056 |
| 1057 |
| 1058 void Assembler::shlr_(Register Rd) { |
| 1059 ASSERT(REGNUM(Rd) <= 15); |
| 1060 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x1 << 0)); |
| 1061 asm_output("shlr R%d", REGNUM(Rd)); |
| 1062 } |
| 1063 |
| 1064 |
| 1065 void Assembler::shlr16_(Register Rd) { |
| 1066 ASSERT(REGNUM(Rd) <= 15); |
| 1067 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x9 << 0)); |
| 1068 asm_output("shlr16 R%d", REGNUM(Rd)); |
| 1069 } |
| 1070 |
| 1071 |
| 1072 void Assembler::shlr2_(Register Rd) { |
| 1073 ASSERT(REGNUM(Rd) <= 15); |
| 1074 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x9 << 0)); |
| 1075 asm_output("shlr2 R%d", REGNUM(Rd)); |
| 1076 } |
| 1077 |
| 1078 |
| 1079 void Assembler::shlr8_(Register Rd) { |
| 1080 ASSERT(REGNUM(Rd) <= 15); |
| 1081 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0x9 << 0)); |
| 1082 asm_output("shlr8 R%d", REGNUM(Rd)); |
| 1083 } |
| 1084 |
| 1085 |
| 1086 void Assembler::sleep_() { |
| 1087 emit((0x0 << 12) | (0x0 << 8) | (0x1 << 4) | (0xB << 0)); |
| 1088 asm_output("sleep"); |
| 1089 } |
| 1090 |
| 1091 |
| 1092 void Assembler::stc_SR_(Register Rd) { |
| 1093 ASSERT(REGNUM(Rd) <= 15); |
| 1094 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x2 << 0)); |
| 1095 asm_output("stc_SR R%d", REGNUM(Rd)); |
| 1096 } |
| 1097 |
| 1098 |
| 1099 void Assembler::stc_GBR_(Register Rd) { |
| 1100 ASSERT(REGNUM(Rd) <= 15); |
| 1101 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0x2 << 0)); |
| 1102 asm_output("stc_GBR R%d", REGNUM(Rd)); |
| 1103 } |
| 1104 |
| 1105 |
| 1106 void Assembler::stc_VBR_(Register Rd) { |
| 1107 ASSERT(REGNUM(Rd) <= 15); |
| 1108 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x2 << 0)); |
| 1109 asm_output("stc_VBR R%d", REGNUM(Rd)); |
| 1110 } |
| 1111 |
| 1112 |
| 1113 void Assembler::stc_SSR_(Register Rd) { |
| 1114 ASSERT(REGNUM(Rd) <= 15); |
| 1115 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x3 << 4) | (0x2 << 0)); |
| 1116 asm_output("stc_SSR R%d", REGNUM(Rd)); |
| 1117 } |
| 1118 |
| 1119 |
| 1120 void Assembler::stc_SPC_(Register Rd) { |
| 1121 ASSERT(REGNUM(Rd) <= 15); |
| 1122 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x4 << 4) | (0x2 << 0)); |
| 1123 asm_output("stc_SPC R%d", REGNUM(Rd)); |
| 1124 } |
| 1125 |
| 1126 |
| 1127 void Assembler::stc_SGR_(Register Rd) { |
| 1128 ASSERT(REGNUM(Rd) <= 15); |
| 1129 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x3 << 4) | (0xA << 0)); |
| 1130 asm_output("stc_SGR R%d", REGNUM(Rd)); |
| 1131 } |
| 1132 |
| 1133 |
| 1134 void Assembler::stc_DBR_(Register Rd) { |
| 1135 ASSERT(REGNUM(Rd) <= 15); |
| 1136 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xF << 4) | (0xA << 0)); |
| 1137 asm_output("stc_DBR R%d", REGNUM(Rd)); |
| 1138 } |
| 1139 |
| 1140 |
| 1141 void Assembler::stc_bank_(int imm, Register Rd) { |
| 1142 ASSERT(REGNUM(Rd) <= 15 && SH4_CHECK_RANGE_stc_bank(imm)); |
| 1143 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((imm & 0x7) << 4) | |
| 1144 (0x2 << 0)); |
| 1145 asm_output("stc_bank %d, R%d", imm, REGNUM(Rd)); |
| 1146 } |
| 1147 |
| 1148 |
| 1149 void Assembler::stcl_SR_decRd_(Register Rd) { |
| 1150 ASSERT(REGNUM(Rd) <= 15); |
| 1151 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x3 << 0)); |
| 1152 asm_output("stcl_SR_decRd R%d", REGNUM(Rd)); |
| 1153 } |
| 1154 |
| 1155 |
| 1156 void Assembler::stcl_VBR_decRd_(Register Rd) { |
| 1157 ASSERT(REGNUM(Rd) <= 15); |
| 1158 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x3 << 0)); |
| 1159 asm_output("stcl_VBR_decRd R%d", REGNUM(Rd)); |
| 1160 } |
| 1161 |
| 1162 |
| 1163 void Assembler::stcl_SSR_decRd_(Register Rd) { |
| 1164 ASSERT(REGNUM(Rd) <= 15); |
| 1165 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x3 << 4) | (0x3 << 0)); |
| 1166 asm_output("stcl_SSR_decRd R%d", REGNUM(Rd)); |
| 1167 } |
| 1168 |
| 1169 |
| 1170 void Assembler::stcl_SPC_decRd_(Register Rd) { |
| 1171 ASSERT(REGNUM(Rd) <= 15); |
| 1172 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x4 << 4) | (0x3 << 0)); |
| 1173 asm_output("stcl_SPC_decRd R%d", REGNUM(Rd)); |
| 1174 } |
| 1175 |
| 1176 |
| 1177 void Assembler::stcl_GBR_decRd_(Register Rd) { |
| 1178 ASSERT(REGNUM(Rd) <= 15); |
| 1179 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0x3 << 0)); |
| 1180 asm_output("stcl_GBR_decRd R%d", REGNUM(Rd)); |
| 1181 } |
| 1182 |
| 1183 |
| 1184 void Assembler::stcl_SGR_decRd_(Register Rd) { |
| 1185 ASSERT(REGNUM(Rd) <= 15); |
| 1186 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x3 << 4) | (0x2 << 0)); |
| 1187 asm_output("stcl_SGR_decRd R%d", REGNUM(Rd)); |
| 1188 } |
| 1189 |
| 1190 |
| 1191 void Assembler::stcl_DBR_decRd_(Register Rd) { |
| 1192 ASSERT(REGNUM(Rd) <= 15); |
| 1193 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xF << 4) | (0x2 << 0)); |
| 1194 asm_output("stcl_DBR_decRd R%d", REGNUM(Rd)); |
| 1195 } |
| 1196 |
| 1197 |
| 1198 void Assembler::stcl_bank_decRd_(int imm, Register Rd) { |
| 1199 ASSERT(REGNUM(Rd) <= 15 && SH4_CHECK_RANGE_stcl_bank_decRd(imm)); |
| 1200 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((imm & 0x7) << 4) | |
| 1201 (0x3 << 0)); |
| 1202 asm_output("stcl_bank_decRd %d, R%d", imm, REGNUM(Rd)); |
| 1203 } |
| 1204 |
| 1205 |
| 1206 void Assembler::sts_MACH_(Register Rd) { |
| 1207 ASSERT(REGNUM(Rd) <= 15); |
| 1208 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0xA << 0)); |
| 1209 asm_output("sts_MACH R%d", REGNUM(Rd)); |
| 1210 } |
| 1211 |
| 1212 |
| 1213 void Assembler::sts_MACL_(Register Rd) { |
| 1214 ASSERT(REGNUM(Rd) <= 15); |
| 1215 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0xA << 0)); |
| 1216 asm_output("sts_MACL R%d", REGNUM(Rd)); |
| 1217 } |
| 1218 |
| 1219 |
| 1220 void Assembler::sts_PR_(Register Rd) { |
| 1221 ASSERT(REGNUM(Rd) <= 15); |
| 1222 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0xA << 0)); |
| 1223 asm_output("sts_PR R%d", REGNUM(Rd)); |
| 1224 } |
| 1225 |
| 1226 |
| 1227 void Assembler::sts_FPUL_(Register Rd) { |
| 1228 ASSERT(REGNUM(Rd) <= 15); |
| 1229 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x5 << 4) | (0xA << 0)); |
| 1230 asm_output("sts_FPUL R%d", REGNUM(Rd)); |
| 1231 } |
| 1232 |
| 1233 |
| 1234 void Assembler::sts_FPSCR_(Register Rd) { |
| 1235 ASSERT(REGNUM(Rd) <= 15); |
| 1236 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x6 << 4) | (0xA << 0)); |
| 1237 asm_output("sts_FPSCR R%d", REGNUM(Rd)); |
| 1238 } |
| 1239 |
| 1240 |
| 1241 void Assembler::stsl_MACH_decRd_(Register Rd) { |
| 1242 ASSERT(REGNUM(Rd) <= 15); |
| 1243 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x2 << 0)); |
| 1244 asm_output("stsl_MACH_decRd R%d", REGNUM(Rd)); |
| 1245 } |
| 1246 |
| 1247 |
| 1248 void Assembler::stsl_MACL_decRd_(Register Rd) { |
| 1249 ASSERT(REGNUM(Rd) <= 15); |
| 1250 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0x2 << 0)); |
| 1251 asm_output("stsl_MACL_decRd R%d", REGNUM(Rd)); |
| 1252 } |
| 1253 |
| 1254 |
| 1255 void Assembler::stsl_PR_decRd_(Register Rd) { |
| 1256 ASSERT(REGNUM(Rd) <= 15); |
| 1257 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x2 << 0)); |
| 1258 asm_output("stsl_PR_decRd R%d", REGNUM(Rd)); |
| 1259 } |
| 1260 |
| 1261 |
| 1262 void Assembler::stsl_FPUL_decRd_(Register Rd) { |
| 1263 ASSERT(REGNUM(Rd) <= 15); |
| 1264 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x5 << 4) | (0x2 << 0)); |
| 1265 asm_output("stsl_FPUL_decRd R%d", REGNUM(Rd)); |
| 1266 } |
| 1267 |
| 1268 |
| 1269 void Assembler::stsl_FPSCR_decRd_(Register Rd) { |
| 1270 ASSERT(REGNUM(Rd) <= 15); |
| 1271 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x6 << 4) | (0x2 << 0)); |
| 1272 asm_output("stsl_FPSCR_decRd R%d", REGNUM(Rd)); |
| 1273 } |
| 1274 |
| 1275 |
| 1276 void Assembler::sub_(Register Rs, Register Rd) { |
| 1277 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1278 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1279 (0x8 << 0)); |
| 1280 asm_output("sub R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1281 } |
| 1282 |
| 1283 |
| 1284 void Assembler::subc_(Register Rs, Register Rd) { |
| 1285 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1286 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1287 (0xA << 0)); |
| 1288 asm_output("subc R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1289 } |
| 1290 |
| 1291 |
| 1292 void Assembler::subv_(Register Rs, Register Rd) { |
| 1293 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1294 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1295 (0xB << 0)); |
| 1296 asm_output("subv R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1297 } |
| 1298 |
| 1299 |
| 1300 void Assembler::swapb_(Register Rs, Register Rd) { |
| 1301 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1302 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1303 (0x8 << 0)); |
| 1304 asm_output("swapb R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1305 } |
| 1306 |
| 1307 |
| 1308 void Assembler::swapw_(Register Rs, Register Rd) { |
| 1309 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1310 emit((0x6 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1311 (0x9 << 0)); |
| 1312 asm_output("swapw R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1313 } |
| 1314 |
| 1315 |
| 1316 void Assembler::synco_() { |
| 1317 emit((0x0 << 12) | (0x0 << 8) | (0xA << 4) | (0xB << 0)); |
| 1318 asm_output("synco"); |
| 1319 } |
| 1320 |
| 1321 |
| 1322 void Assembler::tasb_indRd_(Register Rd) { |
| 1323 ASSERT(REGNUM(Rd) <= 15); |
| 1324 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0xB << 0)); |
| 1325 asm_output("tasb_indRd R%d", REGNUM(Rd)); |
| 1326 } |
| 1327 |
| 1328 |
| 1329 void Assembler::trapa_imm_(int imm) { |
| 1330 ASSERT(SH4_CHECK_RANGE_trapa_imm(imm)); |
| 1331 emit((0xC << 12) | (0x3 << 8) | ((imm & 0xFF) << 0)); |
| 1332 asm_output("trapa_imm %d", imm); |
| 1333 } |
| 1334 |
| 1335 |
| 1336 void Assembler::tst_imm_R0_(int imm) { |
| 1337 ASSERT(SH4_CHECK_RANGE_tst_imm_R0(imm)); |
| 1338 emit((0xC << 12) | (0x8 << 8) | ((imm & 0xFF) << 0)); |
| 1339 asm_output("tst_imm_R0 %d", imm); |
| 1340 } |
| 1341 |
| 1342 |
| 1343 void Assembler::tst_(Register Rs, Register Rd) { |
| 1344 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1345 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1346 (0x8 << 0)); |
| 1347 asm_output("tst R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1348 } |
| 1349 |
| 1350 |
| 1351 void Assembler::tstb_imm_dispR0GBR_(int imm) { |
| 1352 ASSERT(SH4_CHECK_RANGE_tstb_imm_dispR0GBR(imm)); |
| 1353 emit((0xC << 12) | (0xC << 8) | ((imm & 0xFF) << 0)); |
| 1354 asm_output("tstb_imm_dispR0GBR %d", imm); |
| 1355 } |
| 1356 |
| 1357 |
| 1358 void Assembler::xor_imm_R0_(int imm) { |
| 1359 ASSERT(SH4_CHECK_RANGE_xor_imm_R0(imm)); |
| 1360 emit((0xC << 12) | (0xA << 8) | ((imm & 0xFF) << 0)); |
| 1361 asm_output("xor_imm_R0 %d", imm); |
| 1362 } |
| 1363 |
| 1364 |
| 1365 void Assembler::xor_(Register Rs, Register Rd) { |
| 1366 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1367 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1368 (0xA << 0)); |
| 1369 asm_output("xor R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1370 } |
| 1371 |
| 1372 |
| 1373 void Assembler::xorb_imm_dispR0GBR_(int imm) { |
| 1374 ASSERT(SH4_CHECK_RANGE_xorb_imm_dispR0GBR(imm)); |
| 1375 emit((0xC << 12) | (0xE << 8) | ((imm & 0xFF) << 0)); |
| 1376 asm_output("xorb_imm_dispR0GBR %d", imm); |
| 1377 } |
| 1378 |
| 1379 |
| 1380 void Assembler::xtrct_(Register Rs, Register Rd) { |
| 1381 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1382 emit((0x2 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1383 (0xD << 0)); |
| 1384 asm_output("xtrct R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1385 } |
| 1386 |
| 1387 |
| 1388 void Assembler::dt_(Register Rd) { |
| 1389 ASSERT(REGNUM(Rd) <= 15); |
| 1390 emit((0x4 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0x0 << 0)); |
| 1391 asm_output("dt R%d", REGNUM(Rd)); |
| 1392 } |
| 1393 |
| 1394 |
| 1395 void Assembler::dmulsl_(Register Rs, Register Rd) { |
| 1396 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1397 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1398 (0xD << 0)); |
| 1399 asm_output("dmulsl R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1400 } |
| 1401 |
| 1402 |
| 1403 void Assembler::dmulul_(Register Rs, Register Rd) { |
| 1404 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1405 emit((0x3 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1406 (0x5 << 0)); |
| 1407 asm_output("dmulul R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1408 } |
| 1409 |
| 1410 |
| 1411 void Assembler::macl_incRs_incRd_(Register Rs, Register Rd) { |
| 1412 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1413 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1414 (0xF << 0)); |
| 1415 asm_output("macl_incRs_incRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1416 } |
| 1417 |
| 1418 |
| 1419 void Assembler::braf_(Register Rd) { |
| 1420 ASSERT(REGNUM(Rd) <= 15); |
| 1421 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0x3 << 0)); |
| 1422 asm_output("braf R%d", REGNUM(Rd)); |
| 1423 } |
| 1424 |
| 1425 |
| 1426 void Assembler::bsrf_(Register Rd) { |
| 1427 ASSERT(REGNUM(Rd) <= 15); |
| 1428 emit((0x0 << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0x3 << 0)); |
| 1429 asm_output("bsrf R%d", REGNUM(Rd)); |
| 1430 } |
| 1431 |
| 1432 |
| 1433 void Assembler::fabs_(SwVfpRegister Rd) { |
| 1434 ASSERT(REGNUM(Rd) <= 15); |
| 1435 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x5 << 4) | (0xD << 0)); |
| 1436 asm_output("fabs R%d", REGNUM(Rd)); |
| 1437 } |
| 1438 |
| 1439 |
| 1440 void Assembler::fabs_double_(DwVfpRegister Rd) { |
| 1441 ASSERT((REGNUM(Rd)) <= 15 && !((REGNUM(Rd)) & 0x1)); |
| 1442 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x5 << 4) | (0xD << 0)); |
| 1443 asm_output("fabs_double R%d", REGNUM(Rd)); |
| 1444 } |
| 1445 |
| 1446 |
| 1447 void Assembler::fadd_(SwVfpRegister Rs, SwVfpRegister Rd) { |
| 1448 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1449 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1450 (0x0 << 0)); |
| 1451 asm_output("fadd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1452 } |
| 1453 |
| 1454 |
| 1455 void Assembler::fadd_double_(DwVfpRegister Rs, DwVfpRegister Rd) { |
| 1456 ASSERT(REGNUM(Rd) <= 15 && !(REGNUM(Rd) & 0x1) && |
| 1457 REGNUM(Rs) <= 15 && !(REGNUM(Rs) & 0x1)); |
| 1458 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1459 (0x0 << 0)); |
| 1460 asm_output("fadd_double R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1461 } |
| 1462 |
| 1463 |
| 1464 void Assembler::fcmpeq_(SwVfpRegister Rs, SwVfpRegister Rd) { |
| 1465 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1466 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1467 (0x4 << 0)); |
| 1468 asm_output("fcmpeq R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1469 } |
| 1470 |
| 1471 |
| 1472 void Assembler::fcmpeq_double_(DwVfpRegister Rs, DwVfpRegister Rd) { |
| 1473 ASSERT(REGNUM(Rd) <= 15 && !(REGNUM(Rd) & 0x1) && |
| 1474 REGNUM(Rs) <= 15 && !(REGNUM(Rs) & 0x1)); |
| 1475 emit((0xF << 12) | (((REGNUM(Rd)) & 0xF) << 8) | |
| 1476 (((REGNUM(Rs)) & 0xF) << 4) | (0x4 << 0)); |
| 1477 asm_output("fcmpeq_double R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1478 } |
| 1479 |
| 1480 |
| 1481 void Assembler::fcmpgt_(SwVfpRegister Rs, SwVfpRegister Rd) { |
| 1482 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1483 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1484 (0x5 << 0)); |
| 1485 asm_output("fcmpgt R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1486 } |
| 1487 |
| 1488 |
| 1489 void Assembler::fcmpgt_double_(DwVfpRegister Rs, DwVfpRegister Rd) { |
| 1490 ASSERT(REGNUM(Rd) <= 15 && !(REGNUM(Rd) & 0x1) && |
| 1491 REGNUM(Rs) <= 15 && !(REGNUM(Rs) & 0x1)); |
| 1492 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1493 (0x5 << 0)); |
| 1494 asm_output("fcmpgt_double R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1495 } |
| 1496 |
| 1497 |
| 1498 void Assembler::fcnvds_double_FPUL_(DwVfpRegister Rd) { |
| 1499 ASSERT(!(REGNUM(Rd) & 0x1)); |
| 1500 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xB << 4) | (0xD << 0)); |
| 1501 asm_output("fcnvds_double_FPUL R%d", REGNUM(Rd)); |
| 1502 } |
| 1503 |
| 1504 |
| 1505 void Assembler::fcnvsd_FPUL_double_(DwVfpRegister Rd) { |
| 1506 ASSERT(!(REGNUM(Rd) & 0x1)); |
| 1507 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xA << 4) | (0xD << 0)); |
| 1508 asm_output("fcnvsd_FPUL_double R%d", REGNUM(Rd)); |
| 1509 } |
| 1510 |
| 1511 |
| 1512 void Assembler::fdiv_(SwVfpRegister Rs, SwVfpRegister Rd) { |
| 1513 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1514 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1515 (0x3 << 0)); |
| 1516 asm_output("fdiv R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1517 } |
| 1518 |
| 1519 |
| 1520 void Assembler::fdiv_double_(DwVfpRegister Rs, DwVfpRegister Rd) { |
| 1521 ASSERT(REGNUM(Rd) <= 15 && !(REGNUM(Rd) & 0x1) && |
| 1522 REGNUM(Rs) <= 15 && !(REGNUM(Rs) & 0x1)); |
| 1523 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1524 (0x3 << 0)); |
| 1525 asm_output("fdiv_double R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1526 } |
| 1527 |
| 1528 |
| 1529 void Assembler::fipr_(SwVfpRegister Rs, SwVfpRegister Rd) { |
| 1530 ASSERT(!((REGNUM(Rd) & 0x3) || (REGNUM(Rs) & 0x3))); |
| 1531 emit((0xF << 12) | ((((REGNUM(Rd) & 0xF) << 2) | |
| 1532 ((REGNUM(Rs) & 0xF) >> 2)) << 8) | (0xE << 4) | (0xD << 0)); |
| 1533 asm_output("fipr R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1534 } |
| 1535 |
| 1536 |
| 1537 void Assembler::fldi0_(SwVfpRegister Rd) { |
| 1538 ASSERT(REGNUM(Rd) <= 15); |
| 1539 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x8 << 4) | (0xD << 0)); |
| 1540 asm_output("fldi0 R%d", REGNUM(Rd)); |
| 1541 } |
| 1542 |
| 1543 |
| 1544 void Assembler::fldi1_(SwVfpRegister Rd) { |
| 1545 ASSERT(REGNUM(Rd) <= 15); |
| 1546 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x9 << 4) | (0xD << 0)); |
| 1547 asm_output("fldi1 R%d", REGNUM(Rd)); |
| 1548 } |
| 1549 |
| 1550 |
| 1551 void Assembler::flds_FPUL_(SwVfpRegister Rd) { |
| 1552 ASSERT(REGNUM(Rd) <= 15); |
| 1553 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x1 << 4) | (0xD << 0)); |
| 1554 asm_output("flds_FPUL R%d", REGNUM(Rd)); |
| 1555 } |
| 1556 |
| 1557 |
| 1558 void Assembler::float_FPUL_(SwVfpRegister Rd) { |
| 1559 ASSERT(REGNUM(Rd) <= 15); |
| 1560 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x2 << 4) | (0xD << 0)); |
| 1561 asm_output("float_FPUL R%d", REGNUM(Rd)); |
| 1562 } |
| 1563 |
| 1564 |
| 1565 void Assembler::float_FPUL_double_(DwVfpRegister Rd) { |
| 1566 ASSERT(REGNUM(Rd) <= 15 && !(REGNUM(Rd) & 0x1)); |
| 1567 emit((0xF << 12) | (((REGNUM(Rd)) & 0xF) << 8) | (0x2 << 4) | (0xD << 0)); |
| 1568 asm_output("float_FPUL_double R%d", REGNUM(Rd)); |
| 1569 } |
| 1570 |
| 1571 |
| 1572 void Assembler::fmac_(SwVfpRegister Rs, SwVfpRegister Rd) { |
| 1573 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1574 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1575 (0xE << 0)); |
| 1576 asm_output("fmac R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1577 } |
| 1578 |
| 1579 |
| 1580 void Assembler::fmov_(SwVfpRegister Rs, SwVfpRegister Rd) { |
| 1581 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1582 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1583 (0xC << 0)); |
| 1584 asm_output("fmov R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1585 } |
| 1586 |
| 1587 |
| 1588 void Assembler::fmov_Xdouble_Xdouble_(DwVfpRegister Rs, DwVfpRegister Rd) { |
| 1589 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1590 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1591 (0xC << 0)); |
| 1592 asm_output("fmov_Xdouble_Xdouble R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1593 } |
| 1594 |
| 1595 |
| 1596 void Assembler::fmov_indRs_(Register Rs, SwVfpRegister Rd) { |
| 1597 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1598 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1599 (0x8 << 0)); |
| 1600 asm_output("fmov_indRs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1601 } |
| 1602 |
| 1603 |
| 1604 void Assembler::fmov_indRs_Xdouble_(Register Rs, DwVfpRegister Rd) { |
| 1605 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1606 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1607 (0x8 << 0)); |
| 1608 asm_output("fmov_indRs_Xdouble R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1609 } |
| 1610 |
| 1611 |
| 1612 void Assembler::fmov_indRd_(SwVfpRegister Rs, Register Rd) { |
| 1613 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1614 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1615 (0xA << 0)); |
| 1616 asm_output("fmov_indRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1617 } |
| 1618 |
| 1619 |
| 1620 void Assembler::fmov_Xdouble_indRd_(DwVfpRegister Rs, Register Rd) { |
| 1621 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1622 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1623 (0xA << 0)); |
| 1624 asm_output("fmov_Xdouble_indRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1625 } |
| 1626 |
| 1627 |
| 1628 void Assembler::fmov_incRs_(Register Rs, SwVfpRegister Rd) { |
| 1629 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1630 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1631 (0x9 << 0)); |
| 1632 asm_output("fmov_incRs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1633 } |
| 1634 |
| 1635 |
| 1636 void Assembler::fmov_decRd_(SwVfpRegister Rs, Register Rd) { |
| 1637 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1638 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1639 (0xB << 0)); |
| 1640 asm_output("fmov_decRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1641 } |
| 1642 |
| 1643 |
| 1644 void Assembler::fmov_dispR0Rs_(Register Rs, SwVfpRegister Rd) { |
| 1645 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1646 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1647 (0x6 << 0)); |
| 1648 asm_output("fmov_dispR0Rs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1649 } |
| 1650 |
| 1651 |
| 1652 void Assembler::fmov_dispR0Rs_Xdouble_(Register Rs, DwVfpRegister Rd) { |
| 1653 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1654 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1655 (0x6 << 0)); |
| 1656 asm_output("fmov_dispR0Rs_Xdouble R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1657 } |
| 1658 |
| 1659 |
| 1660 void Assembler::fmov_dispR0Rd_(SwVfpRegister Rs, Register Rd) { |
| 1661 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1662 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1663 (0x7 << 0)); |
| 1664 asm_output("fmov_dispR0Rd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1665 } |
| 1666 |
| 1667 |
| 1668 void Assembler::fmov_Xdouble_dispR0Rd_(DwVfpRegister Rs, Register Rd) { |
| 1669 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1670 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1671 (0x7 << 0)); |
| 1672 asm_output("fmov_Xdouble_dispR0Rd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1673 } |
| 1674 |
| 1675 |
| 1676 void Assembler::fmovd_indRs_Xdouble_(Register Rs, DwVfpRegister Rd) { |
| 1677 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1678 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1679 (0x8 << 0)); |
| 1680 asm_output("fmovd_indRs_Xdouble R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1681 } |
| 1682 |
| 1683 |
| 1684 void Assembler::fmovd_Xdouble_indRd_(DwVfpRegister Rs, Register Rd) { |
| 1685 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1686 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1687 (0xA << 0)); |
| 1688 asm_output("fmovd_Xdouble_indRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1689 } |
| 1690 |
| 1691 |
| 1692 void Assembler::fmovd_incRs_Xdouble_(Register Rs, DwVfpRegister Rd) { |
| 1693 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1694 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1695 (0x9 << 0)); |
| 1696 asm_output("fmovd_incRs_Xdouble R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1697 } |
| 1698 |
| 1699 |
| 1700 void Assembler::fmovd_Xdouble_decRd_(DwVfpRegister Rs, Register Rd) { |
| 1701 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1702 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1703 (0xB << 0)); |
| 1704 asm_output("fmovd_Xdouble_decRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1705 } |
| 1706 |
| 1707 |
| 1708 void Assembler::fmovd_dispR0Rs_Xdouble_(Register Rs, DwVfpRegister Rd) { |
| 1709 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1710 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1711 (0x6 << 0)); |
| 1712 asm_output("fmovd_dispR0Rs_Xdouble R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1713 } |
| 1714 |
| 1715 |
| 1716 void Assembler::fmovd_Xdouble_dispR0Rd_(DwVfpRegister Rs, Register Rd) { |
| 1717 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1718 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1719 (0x7 << 0)); |
| 1720 asm_output("fmovd_Xdouble_dispR0Rd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1721 } |
| 1722 |
| 1723 |
| 1724 void Assembler::fmovs_indRs_(Register Rs, SwVfpRegister Rd) { |
| 1725 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1726 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1727 (0x8 << 0)); |
| 1728 asm_output("fmovs_indRs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1729 } |
| 1730 |
| 1731 |
| 1732 void Assembler::fmovs_indRd_(SwVfpRegister Rs, Register Rd) { |
| 1733 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1734 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1735 (0xA << 0)); |
| 1736 asm_output("fmovs_indRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1737 } |
| 1738 |
| 1739 |
| 1740 void Assembler::fmovs_incRs_(Register Rs, SwVfpRegister Rd) { |
| 1741 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1742 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1743 (0x9 << 0)); |
| 1744 asm_output("fmovs_incRs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1745 } |
| 1746 |
| 1747 |
| 1748 void Assembler::fmovs_decRd_(SwVfpRegister Rs, Register Rd) { |
| 1749 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1750 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1751 (0xB << 0)); |
| 1752 asm_output("fmovs_decRd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1753 } |
| 1754 |
| 1755 |
| 1756 void Assembler::fmovs_dispR0Rs_(Register Rs, SwVfpRegister Rd) { |
| 1757 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1758 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1759 (0x6 << 0)); |
| 1760 asm_output("fmovs_dispR0Rs R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1761 } |
| 1762 |
| 1763 |
| 1764 void Assembler::fmovs_dispR0Rd_(SwVfpRegister Rs, Register Rd) { |
| 1765 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1766 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1767 (0x7 << 0)); |
| 1768 asm_output("fmovs_dispR0Rd R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1769 } |
| 1770 |
| 1771 |
| 1772 void Assembler::fmul_(SwVfpRegister Rs, SwVfpRegister Rd) { |
| 1773 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1774 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1775 (0x2 << 0)); |
| 1776 asm_output("fmul R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1777 } |
| 1778 |
| 1779 |
| 1780 void Assembler::fmul_double_(DwVfpRegister Rs, DwVfpRegister Rd) { |
| 1781 ASSERT(REGNUM(Rd) <= 15 && !(REGNUM(Rd) & 0x1) && |
| 1782 REGNUM(Rs) <= 15 && !(REGNUM(Rs) & 0x1)); |
| 1783 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1784 (0x2 << 0)); |
| 1785 asm_output("fmul_double R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1786 } |
| 1787 |
| 1788 |
| 1789 void Assembler::fneg_(SwVfpRegister Rd) { |
| 1790 ASSERT(REGNUM(Rd) <= 15); |
| 1791 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x4 << 4) | (0xD << 0)); |
| 1792 asm_output("fneg R%d", REGNUM(Rd)); |
| 1793 } |
| 1794 |
| 1795 |
| 1796 void Assembler::fneg_double_(DwVfpRegister Rd) { |
| 1797 ASSERT(REGNUM(Rd) <= 15 && !(REGNUM(Rd) & 0x1)); |
| 1798 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x4 << 4) | (0xD << 0)); |
| 1799 asm_output("fneg_double R%d", REGNUM(Rd)); |
| 1800 } |
| 1801 |
| 1802 |
| 1803 void Assembler::fpchg_() { |
| 1804 emit((0xF << 12) | (0x7 << 8) | (0xF << 4) | (0xD << 0)); |
| 1805 asm_output("fpchg"); |
| 1806 } |
| 1807 |
| 1808 |
| 1809 void Assembler::frchg_() { |
| 1810 emit((0xF << 12) | (0xB << 8) | (0xF << 4) | (0xD << 0)); |
| 1811 asm_output("frchg"); |
| 1812 } |
| 1813 |
| 1814 |
| 1815 void Assembler::fsca_FPUL_double_(DwVfpRegister Rd) { |
| 1816 ASSERT(!(REGNUM(Rd) & 0x1)); |
| 1817 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0xF << 4) | |
| 1818 (0xD << 0)); |
| 1819 asm_output("fsca_FPUL_double R%d", REGNUM(Rd)); |
| 1820 } |
| 1821 |
| 1822 |
| 1823 void Assembler::fschg_() { |
| 1824 emit((0xF << 12) | (0x3 << 8) | (0xF << 4) | (0xD << 0)); |
| 1825 asm_output("fschg"); |
| 1826 } |
| 1827 |
| 1828 |
| 1829 void Assembler::fsqrt_(SwVfpRegister Rd) { |
| 1830 ASSERT(REGNUM(Rd) <= 15); |
| 1831 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x6 << 4) | (0xD << 0)); |
| 1832 asm_output("fsqrt R%d", REGNUM(Rd)); |
| 1833 } |
| 1834 |
| 1835 |
| 1836 void Assembler::fsqrt_double_(DwVfpRegister Rd) { |
| 1837 ASSERT(REGNUM(Rd) <= 15 && !(REGNUM(Rd) & 0x1)); |
| 1838 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x6 << 4) | (0xD << 0)); |
| 1839 asm_output("fsqrt_double R%d", REGNUM(Rd)); |
| 1840 } |
| 1841 |
| 1842 |
| 1843 void Assembler::fsrra_(SwVfpRegister Rd) { |
| 1844 ASSERT(REGNUM(Rd) <= 15); |
| 1845 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x7 << 4) | (0xD << 0)); |
| 1846 asm_output("fsrra R%d", REGNUM(Rd)); |
| 1847 } |
| 1848 |
| 1849 |
| 1850 void Assembler::fsts_FPUL_(SwVfpRegister Rd) { |
| 1851 ASSERT(REGNUM(Rd) <= 15); |
| 1852 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x0 << 4) | (0xD << 0)); |
| 1853 asm_output("fsts_FPUL R%d", REGNUM(Rd)); |
| 1854 } |
| 1855 |
| 1856 |
| 1857 void Assembler::fsub_(SwVfpRegister Rs, SwVfpRegister Rd) { |
| 1858 ASSERT(REGNUM(Rd) <= 15 && REGNUM(Rs) <= 15); |
| 1859 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1860 (0x1 << 0)); |
| 1861 asm_output("fsub R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1862 } |
| 1863 |
| 1864 |
| 1865 void Assembler::fsub_double_(DwVfpRegister Rs, DwVfpRegister Rd) { |
| 1866 ASSERT(REGNUM(Rd) <= 15 && !(REGNUM(Rd) & 0x1) && |
| 1867 REGNUM(Rs) <= 15 && !(REGNUM(Rs) & 0x1)); |
| 1868 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | ((REGNUM(Rs) & 0xF) << 4) | |
| 1869 (0x1 << 0)); |
| 1870 asm_output("fsub_double R%d, R%d", REGNUM(Rs), REGNUM(Rd)); |
| 1871 } |
| 1872 |
| 1873 |
| 1874 void Assembler::ftrc_FPUL_(SwVfpRegister Rd) { |
| 1875 ASSERT(REGNUM(Rd) <= 15); |
| 1876 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x3 << 4) | (0xD << 0)); |
| 1877 asm_output("ftrc_FPUL R%d", REGNUM(Rd)); |
| 1878 } |
| 1879 |
| 1880 |
| 1881 void Assembler::ftrc_double_FPUL_(DwVfpRegister Rd) { |
| 1882 ASSERT(REGNUM(Rd) <= 15 && !(REGNUM(Rd) & 0x1)); |
| 1883 emit((0xF << 12) | ((REGNUM(Rd) & 0xF) << 8) | (0x3 << 4) | (0xD << 0)); |
| 1884 asm_output("ftrc_double_FPUL R%d", REGNUM(Rd)); |
| 1885 } |
| 1886 |
| 1887 |
| 1888 void Assembler::ftrv_(Register Rd) { |
| 1889 ASSERT(!(REGNUM(Rd) & 0x3)); |
| 1890 emit((0xF << 12) | ((((REGNUM(Rd) & 0xF) << 2) | 0x1) << 8) | (0xF << 4) | |
| 1891 (0xD << 0)); |
| 1892 asm_output("ftrv R%d", REGNUM(Rd)); |
| 1893 } |
| 1894 |
| 1895 } } // namespace v8::internal |
| 1896 |
| 1897 #endif // V8_TARGET_ARCH_SH4 |
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