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| 1 /* |
| 2 * Disassemble SuperH instructions. |
| 3 * |
| 4 * Copyright (C) 1999 kaz Kojima |
| 5 * Copyright (C) 2008 Paul Mundt |
| 6 * |
| 7 * This file is subject to the terms and conditions of the GNU General Public |
| 8 * License. See the file "COPYING" in the main directory of this archive |
| 9 * for more details. |
| 10 */ |
| 11 /*COMMENTED(#include <linux/kernel.h>*/ |
| 12 /*COMMENTED(#include <linux/string.h>*/ |
| 13 /*COMMENTED(#include <linux/uaccess.h>*/ |
| 14 |
| 15 #if !defined(V8_TARGET_ARCH_SH4) || defined(V8_IN_TYPE_DECLS) |
| 16 |
| 17 /* |
| 18 * Format of an instruction in memory. |
| 19 */ |
| 20 typedef enum { |
| 21 HEX_0, HEX_1, HEX_2, HEX_3, HEX_4, HEX_5, HEX_6, HEX_7, |
| 22 HEX_8, HEX_9, HEX_A, HEX_B, HEX_C, HEX_D, HEX_E, HEX_F, |
| 23 REG_N, REG_M, REG_NM, REG_B, |
| 24 BRANCH_12, BRANCH_8, |
| 25 DISP_8, DISP_4, |
| 26 IMM_4, IMM_4BY2, IMM_4BY4, PCRELIMM_8BY2, PCRELIMM_8BY4, |
| 27 IMM_8, IMM_8BY2, IMM_8BY4/*COMMENTED(,)*/ |
| 28 } sh_nibble_type; |
| 29 |
| 30 typedef enum { |
| 31 A_END, A_BDISP12, A_BDISP8, |
| 32 A_DEC_M, A_DEC_N, |
| 33 A_DISP_GBR, A_DISP_PC, A_DISP_REG_M, A_DISP_REG_N, |
| 34 A_GBR, |
| 35 A_IMM, |
| 36 A_INC_M, A_INC_N, |
| 37 A_IND_M, A_IND_N, A_IND_R0_REG_M, A_IND_R0_REG_N, |
| 38 A_MACH, A_MACL, |
| 39 A_PR, A_R0, A_R0_GBR, A_REG_M, A_REG_N, A_REG_B, |
| 40 A_SR, A_VBR, A_SSR, A_SPC, A_SGR, A_DBR, |
| 41 F_REG_N, F_REG_M, D_REG_N, D_REG_M, |
| 42 X_REG_N, /* Only used for argument parsing */ |
| 43 X_REG_M, /* Only used for argument parsing */ |
| 44 DX_REG_N, DX_REG_M, V_REG_N, V_REG_M, |
| 45 FD_REG_N, |
| 46 XMTRX_M4, |
| 47 F_FR0, |
| 48 FPUL_N, FPUL_M, FPSCR_N, FPSCR_M/*COMMENTED(,)*/ |
| 49 } sh_arg_type; |
| 50 |
| 51 static struct sh_opcode_info { |
| 52 /*ADDED(*/const/*)*/ char *name; |
| 53 sh_arg_type arg[7]; |
| 54 sh_nibble_type nibbles[4]; |
| 55 } sh_table[] = { |
| 56 {"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}}, |
| 57 {"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}}, |
| 58 {"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}}, |
| 59 {"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}}, |
| 60 {"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}}, |
| 61 {"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}}, |
| 62 {"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}}, |
| 63 {"bra",{A_BDISP12},{HEX_A,BRANCH_12}}, |
| 64 {"bsr",{A_BDISP12},{HEX_B,BRANCH_12}}, |
| 65 {"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}}, |
| 66 {"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}}, |
| 67 {"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}}, |
| 68 {"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}}, |
| 69 {"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}}, |
| 70 {"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}}, |
| 71 {"clrmac",{/*REPLACED(0,*/A_END/*)*/},{HEX_0,HEX_0,HEX_2,HEX_8}}, |
| 72 {"clrs",{/*REPLACED(0,*/A_END/*)*/},{HEX_0,HEX_0,HEX_4,HEX_8}}, |
| 73 {"clrt",{/*REPLACED(0,*/A_END/*)*/},{HEX_0,HEX_0,HEX_0,HEX_8}}, |
| 74 {"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}}, |
| 75 {"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}}, |
| 76 {"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}}, |
| 77 {"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}}, |
| 78 {"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}}, |
| 79 {"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}}, |
| 80 {"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}}, |
| 81 {"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}}, |
| 82 {"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}}, |
| 83 {"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}}, |
| 84 {"div0u",{/*REPLACED(0,*/A_END/*)*/},{HEX_0,HEX_0,HEX_1,HEX_9}}, |
| 85 {"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}}, |
| 86 {"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}}, |
| 87 {"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}}, |
| 88 {"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}}, |
| 89 {"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}}, |
| 90 {"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}}, |
| 91 {"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}}, |
| 92 {"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}}, |
| 93 {"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}}, |
| 94 {"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}}, |
| 95 {"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}}, |
| 96 {"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}}, |
| 97 {"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_E}}, |
| 98 {"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}}, |
| 99 {"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}}, |
| 100 {"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}}, |
| 101 {"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}}, |
| 102 {"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}}, |
| 103 {"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}}, |
| 104 {"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_7}}, |
| 105 {"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}}, |
| 106 {"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}}, |
| 107 {"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}}, |
| 108 {"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}}, |
| 109 {"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}}, |
| 110 {"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}}, |
| 111 {"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}}, |
| 112 {"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}}, |
| 113 {"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}}, |
| 114 {"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}}, |
| 115 {"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}}, |
| 116 {"ldtlb",{/*REPLACED(0,*/A_END/*)*/},{HEX_0,HEX_0,HEX_3,HEX_8}}, |
| 117 {"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}}, |
| 118 {"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}}, |
| 119 {"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}}, |
| 120 {"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}}, |
| 121 {"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}}, |
| 122 {"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}}, |
| 123 {"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}}, |
| 124 {"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}}, |
| 125 {"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}}, |
| 126 {"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}}, |
| 127 {"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}}, |
| 128 {"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}}, |
| 129 {"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}}, |
| 130 {"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}}, |
| 131 {"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}}, |
| 132 {"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}}, |
| 133 {"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}}, |
| 134 {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}}, |
| 135 {"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}}, |
| 136 {"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}}, |
| 137 {"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}}, |
| 138 {"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}}, |
| 139 {"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}}, |
| 140 {"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}}, |
| 141 {"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}}, |
| 142 {"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}}, |
| 143 {"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}}, |
| 144 {"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}}, |
| 145 {"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}}, |
| 146 {"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}}, |
| 147 {"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}}, |
| 148 {"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}}, |
| 149 {"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}}, |
| 150 {"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}}, |
| 151 {"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}}, |
| 152 {"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}}, |
| 153 {"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}}, |
| 154 {"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}}, |
| 155 {"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}}, |
| 156 {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, |
| 157 {"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}}, |
| 158 {"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}}, |
| 159 {"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}}, |
| 160 {"nop",{/*REPLACED(0,*/A_END/*)*/},{HEX_0,HEX_0,HEX_0,HEX_9}}, |
| 161 {"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}}, |
| 162 {"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}}, |
| 163 {"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}}, |
| 164 {"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}}, |
| 165 {"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}}, |
| 166 {"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}}, |
| 167 {"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}}, |
| 168 {"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}}, |
| 169 {"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}}, |
| 170 {"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}}, |
| 171 {"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}}, |
| 172 {"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}}, |
| 173 {"rte",{/*REPLACED(0,*/A_END/*)*/},{HEX_0,HEX_0,HEX_2,HEX_B}}, |
| 174 {"rts",{/*REPLACED(0,*/A_END/*)*/},{HEX_0,HEX_0,HEX_0,HEX_B}}, |
| 175 {"sets",{/*REPLACED(0,*/A_END/*)*/},{HEX_0,HEX_0,HEX_5,HEX_8}}, |
| 176 {"sett",{/*REPLACED(0,*/A_END/*)*/},{HEX_0,HEX_0,HEX_1,HEX_8}}, |
| 177 {"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}}, |
| 178 {"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}}, |
| 179 {"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}}, |
| 180 {"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}}, |
| 181 {"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}}, |
| 182 {"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}}, |
| 183 {"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}}, |
| 184 {"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}}, |
| 185 {"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}}, |
| 186 {"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}}, |
| 187 {"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}}, |
| 188 {"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}}, |
| 189 {"sleep",{/*REPLACED(0,*/A_END/*)*/},{HEX_0,HEX_0,HEX_1,HEX_B}}, |
| 190 {"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}}, |
| 191 {"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}}, |
| 192 {"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}}, |
| 193 {"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}}, |
| 194 {"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}}, |
| 195 {"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}}, |
| 196 {"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}}, |
| 197 {"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}}, |
| 198 {"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}}, |
| 199 {"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}}, |
| 200 {"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}}, |
| 201 {"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}}, |
| 202 {"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}}, |
| 203 {"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}}, |
| 204 {"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}}, |
| 205 {"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}}, |
| 206 {"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}}, |
| 207 {"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}}, |
| 208 {"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}}, |
| 209 {"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}}, |
| 210 {"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}}, |
| 211 {"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}}, |
| 212 {"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}}, |
| 213 {"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}}, |
| 214 {"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}}, |
| 215 {"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}}, |
| 216 {"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}}, |
| 217 {"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}}, |
| 218 {"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}}, |
| 219 {"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}}, |
| 220 {"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}}, |
| 221 {"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}}, |
| 222 {"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}}, |
| 223 {"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}}, |
| 224 {"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}}, |
| 225 {"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}}, |
| 226 {"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}}, |
| 227 {"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}}, |
| 228 {"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}}, |
| 229 {"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}}, |
| 230 {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, |
| 231 {"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}}, |
| 232 {"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}}, |
| 233 {"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}}, |
| 234 {"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}}, |
| 235 {"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}}, |
| 236 {"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}}, |
| 237 {"fabs",{FD_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}}, |
| 238 {"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}}, |
| 239 {"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}}, |
| 240 {"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}}, |
| 241 {"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}}, |
| 242 {"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}}, |
| 243 {"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}}, |
| 244 {"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}}, |
| 245 {"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}}, |
| 246 {"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}}, |
| 247 {"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}}, |
| 248 {"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}}, |
| 249 {"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}}, |
| 250 {"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}}, |
| 251 {"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}}, |
| 252 {"float",{FPUL_M,FD_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}}, |
| 253 {"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}}, |
| 254 {"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}}, |
| 255 {"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}}, |
| 256 {"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, |
| 257 {"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, |
| 258 {"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, |
| 259 {"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, |
| 260 {"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, |
| 261 {"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, |
| 262 {"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, |
| 263 {"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, |
| 264 {"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, |
| 265 {"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, |
| 266 {"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, |
| 267 {"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, |
| 268 {"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, |
| 269 {"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, |
| 270 {"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, |
| 271 {"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, |
| 272 {"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, |
| 273 {"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, |
| 274 {"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, |
| 275 {"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, |
| 276 {"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, |
| 277 {"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, |
| 278 {"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, |
| 279 {"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, |
| 280 {"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}}, |
| 281 {"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}}, |
| 282 {"fneg",{FD_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}}, |
| 283 {"frchg",{/*REPLACED(0,*/A_END/*)*/},{HEX_F,HEX_B,HEX_F,HEX_D}}, |
| 284 {"fschg",{/*REPLACED(0,*/A_END/*)*/},{HEX_F,HEX_3,HEX_F,HEX_D}}, |
| 285 {"fsqrt",{FD_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}}, |
| 286 {"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}}, |
| 287 {"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}}, |
| 288 {"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}}, |
| 289 {"ftrc",{FD_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}}, |
| 290 {"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}}, |
| 291 { 0 /*ADDED(*/, {}, {}/*)*/}, |
| 292 }; |
| 293 |
| 294 #endif /* !defined(V8_TARGET_ARCH_SH4) || defined(V8_IN_TYPE_DECLS) */ |
| 295 |
| 296 #if !defined(V8_TARGET_ARCH_SH4) || !defined(V8_IN_TYPE_DECLS) |
| 297 |
| 298 #if !defined(V8_TARGET_ARCH_SH4) |
| 299 static void print_sh_insn(u32 memaddr, u16 insn) |
| 300 #else |
| 301 void Decoder::print_sh_insn(u32 memaddr, u16 insn) |
| 302 #endif |
| 303 { |
| 304 int relmask = ~0; |
| 305 int nibs[4] = { (insn >> 12) & 0xf, (insn >> 8) & 0xf, (insn >> 4) & 0xf
, insn & 0xf}; |
| 306 struct sh_opcode_info *op = sh_table; |
| 307 |
| 308 for (; op->name; op++) { |
| 309 int n; |
| 310 int imm = 0; |
| 311 int rn = 0; |
| 312 int rm = 0; |
| 313 int rb = 0; |
| 314 int disp_pc; |
| 315 int disp_pc_addr = 0; |
| 316 |
| 317 for (n = 0; n < 4; n++) { |
| 318 int i = op->nibbles[n]; |
| 319 |
| 320 if (i < 16) { |
| 321 if (nibs[n] == i) |
| 322 continue; |
| 323 goto fail; |
| 324 } |
| 325 switch (i) { |
| 326 case BRANCH_8: |
| 327 imm = (nibs[2] << 4) | (nibs[3]); |
| 328 if (imm & 0x80) |
| 329 imm |= ~0xff; |
| 330 imm = ((char)imm) * 2 + 4 ; |
| 331 goto ok; |
| 332 case BRANCH_12: |
| 333 imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[
3]); |
| 334 if (imm & 0x800) |
| 335 imm |= ~0xfff; |
| 336 imm = imm * 2 + 4; |
| 337 goto ok; |
| 338 case IMM_4: |
| 339 imm = nibs[3]; |
| 340 goto ok; |
| 341 case IMM_4BY2: |
| 342 imm = nibs[3] <<1; |
| 343 goto ok; |
| 344 case IMM_4BY4: |
| 345 imm = nibs[3] <<2; |
| 346 goto ok; |
| 347 case IMM_8: |
| 348 imm = (nibs[2] << 4) | nibs[3]; |
| 349 goto ok; |
| 350 case PCRELIMM_8BY2: |
| 351 imm = ((nibs[2] << 4) | nibs[3]) <<1; |
| 352 relmask = ~1; |
| 353 goto ok; |
| 354 case PCRELIMM_8BY4: |
| 355 imm = ((nibs[2] << 4) | nibs[3]) <<2; |
| 356 relmask = ~3; |
| 357 goto ok; |
| 358 case IMM_8BY2: |
| 359 imm = ((nibs[2] << 4) | nibs[3]) <<1; |
| 360 goto ok; |
| 361 case IMM_8BY4: |
| 362 imm = ((nibs[2] << 4) | nibs[3]) <<2; |
| 363 goto ok; |
| 364 case DISP_8: |
| 365 imm = (nibs[2] << 4) | (nibs[3]); |
| 366 goto ok; |
| 367 case DISP_4: |
| 368 imm = nibs[3]; |
| 369 goto ok; |
| 370 case REG_N: |
| 371 rn = nibs[n]; |
| 372 break; |
| 373 case REG_M: |
| 374 rm = nibs[n]; |
| 375 break; |
| 376 case REG_NM: |
| 377 rn = (nibs[n] & 0xc) >> 2; |
| 378 rm = (nibs[n] & 0x3); |
| 379 break; |
| 380 case REG_B: |
| 381 rb = nibs[n] & 0x07; |
| 382 break; |
| 383 default: |
| 384 return; |
| 385 } |
| 386 } |
| 387 |
| 388 ok: |
| 389 printk("%-8s ", op->name); |
| 390 disp_pc = 0; |
| 391 for (n = 0; n < 6 && op->arg[n] != A_END; n++) { |
| 392 if (n && op->arg[1] != A_END) |
| 393 printk(", "); |
| 394 switch (op->arg[n]) { |
| 395 case A_IMM: |
| 396 printk("#%d", (char)(imm)); |
| 397 break; |
| 398 case A_R0: |
| 399 printk("r0"); |
| 400 break; |
| 401 case A_REG_N: |
| 402 printk("r%d", rn); |
| 403 break; |
| 404 case A_INC_N: |
| 405 printk("@r%d+", rn); |
| 406 break; |
| 407 case A_DEC_N: |
| 408 printk("@-r%d", rn); |
| 409 break; |
| 410 case A_IND_N: |
| 411 printk("@r%d", rn); |
| 412 break; |
| 413 case A_DISP_REG_N: |
| 414 printk("@(%d,r%d)", imm, rn); |
| 415 break; |
| 416 case A_REG_M: |
| 417 printk("r%d", rm); |
| 418 break; |
| 419 case A_INC_M: |
| 420 printk("@r%d+", rm); |
| 421 break; |
| 422 case A_DEC_M: |
| 423 printk("@-r%d", rm); |
| 424 break; |
| 425 case A_IND_M: |
| 426 printk("@r%d", rm); |
| 427 break; |
| 428 case A_DISP_REG_M: |
| 429 printk("@(%d,r%d)", imm, rm); |
| 430 break; |
| 431 case A_REG_B: |
| 432 printk("r%d_bank", rb); |
| 433 break; |
| 434 case A_DISP_PC: |
| 435 disp_pc = 1; |
| 436 disp_pc_addr = imm + 4 + (memaddr & relmask); |
| 437 printk("0x%08x", disp_pc_addr); |
| 438 break; |
| 439 case A_IND_R0_REG_N: |
| 440 printk("@(r0,r%d)", rn); |
| 441 break; |
| 442 case A_IND_R0_REG_M: |
| 443 printk("@(r0,r%d)", rm); |
| 444 break; |
| 445 case A_DISP_GBR: |
| 446 printk("@(%d,gbr)",imm); |
| 447 break; |
| 448 case A_R0_GBR: |
| 449 printk("@(r0,gbr)"); |
| 450 break; |
| 451 case A_BDISP12: |
| 452 case A_BDISP8: |
| 453 printk("0x%08x", imm + memaddr); |
| 454 break; |
| 455 case A_SR: |
| 456 printk("sr"); |
| 457 break; |
| 458 case A_GBR: |
| 459 printk("gbr"); |
| 460 break; |
| 461 case A_VBR: |
| 462 printk("vbr"); |
| 463 break; |
| 464 case A_SSR: |
| 465 printk("ssr"); |
| 466 break; |
| 467 case A_SPC: |
| 468 printk("spc"); |
| 469 break; |
| 470 case A_MACH: |
| 471 printk("mach"); |
| 472 break; |
| 473 case A_MACL: |
| 474 printk("macl"); |
| 475 break; |
| 476 case A_PR: |
| 477 printk("pr"); |
| 478 break; |
| 479 case A_SGR: |
| 480 printk("sgr"); |
| 481 break; |
| 482 case A_DBR: |
| 483 printk("dbr"); |
| 484 break; |
| 485 case FD_REG_N: |
| 486 if (0) |
| 487 goto d_reg_n; |
| 488 case F_REG_N: |
| 489 printk("fr%d", rn); |
| 490 break; |
| 491 case F_REG_M: |
| 492 printk("fr%d", rm); |
| 493 break; |
| 494 case DX_REG_N: |
| 495 if (rn & 1) { |
| 496 printk("xd%d", rn & ~1); |
| 497 break; |
| 498 } |
| 499 d_reg_n: |
| 500 case D_REG_N: |
| 501 printk("dr%d", rn); |
| 502 break; |
| 503 case DX_REG_M: |
| 504 if (rm & 1) { |
| 505 printk("xd%d", rm & ~1); |
| 506 break; |
| 507 } |
| 508 case D_REG_M: |
| 509 printk("dr%d", rm); |
| 510 break; |
| 511 case FPSCR_M: |
| 512 case FPSCR_N: |
| 513 printk("fpscr"); |
| 514 break; |
| 515 case FPUL_M: |
| 516 case FPUL_N: |
| 517 printk("fpul"); |
| 518 break; |
| 519 case F_FR0: |
| 520 printk("fr0"); |
| 521 break; |
| 522 case V_REG_N: |
| 523 printk("fv%d", rn*4); |
| 524 break; |
| 525 case V_REG_M: |
| 526 printk("fv%d", rm*4); |
| 527 break; |
| 528 case XMTRX_M4: |
| 529 printk("xmtrx"); |
| 530 break; |
| 531 default: |
| 532 return; |
| 533 } |
| 534 } |
| 535 |
| 536 if (disp_pc && strcmp(op->name, "mova") != 0) { |
| 537 u32 val; |
| 538 |
| 539 if (relmask == ~1) |
| 540 __get_user(val, (u16 *)disp_pc_addr); |
| 541 else |
| 542 __get_user(val, (u32 *)disp_pc_addr); |
| 543 |
| 544 printk(" ! 0x%08x", val); |
| 545 } |
| 546 |
| 547 return; |
| 548 fail: |
| 549 ; |
| 550 |
| 551 } |
| 552 |
| 553 printk(".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]); |
| 554 } |
| 555 |
| 556 #endif /* !defined(V8_TARGET_ARCH_SH4) || !defined(V8_IN_TYPE_DECLS) */ |
| 557 |
| 558 #if !defined(V8_TARGET_ARCH_SH4) |
| 559 |
| 560 void show_code(struct pt_regs *regs) |
| 561 { |
| 562 unsigned short *pc = (unsigned short *)regs->pc; |
| 563 long i; |
| 564 |
| 565 if (regs->pc & 0x1) |
| 566 return; |
| 567 |
| 568 printk("Code:\n"); |
| 569 |
| 570 for (i = -3 ; i < 6 ; i++) { |
| 571 unsigned short insn; |
| 572 |
| 573 if (__get_user(insn, pc + i)) { |
| 574 printk(" (Bad address in pc)\n"); |
| 575 break; |
| 576 } |
| 577 |
| 578 printk("%s%08lx: ", (i ? " ": "->"), (unsigned long)(pc + i)); |
| 579 print_sh_insn((unsigned long)(pc + i), insn); |
| 580 printk("\n"); |
| 581 } |
| 582 |
| 583 printk("\n"); |
| 584 } |
| 585 |
| 586 #endif /*!V8_TARGET_ARCH_SH4*/ |
| OLD | NEW |
|---|
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