Lower a few basic ARM binops for i{8,16,32,64}.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstARM32 and OperandARM32 classes,
@@ skipping 49 matching lines @@
   assert(Inst->getSrcSize() == 2);
   Variable *Dest = Inst->getDest();
   assert(Dest == Inst->getSrc(0));
   Operand *Src1 = Inst->getSrc(1);
   Str << "\t" << Opcode << "\t";
   Dest->emit(Func);
   Str << ", ";
   Src1->emit(Func);
 }
 
+void emitThreeAddr(const char *Opcode, const Inst *Inst, const Cfg *Func,
+                   bool SetFlags) {
+  if (!ALLOW_DUMP)
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(Inst->getSrcSize() == 2);
+  Variable *Dest = Inst->getDest();
+  Operand *Src0 = Inst->getSrc(0);
+  Operand *Src1 = Inst->getSrc(1);
+  Str << "\t" << Opcode << (SetFlags ? "s" : "") << "\t";
+  Dest->emit(Func);
+  Str << ", ";
+  Src0->emit(Func);
+  Str << ", ";
+  Src1->emit(Func);
+}
+
 OperandARM32Mem::OperandARM32Mem(Cfg * /* Func */, Type Ty, Variable *Base,
                                  ConstantInteger32 *ImmOffset, AddrMode Mode)
     : OperandARM32(kMem, Ty), Base(Base), ImmOffset(ImmOffset), Index(nullptr),
       ShiftOp(kNoShift), ShiftAmt(0), Mode(Mode) {
   // The Neg modes are only needed for Reg +/- Reg.
   assert(!isNegAddrMode());
   NumVars = 1;
   Vars = &this->Base;
 }
 
@@ skipping 59 matching lines @@
   Vars[0] = Reg;
   if (ShiftVar)
     Vars[1] = ShiftVar;
 }
 
 InstARM32Ldr::InstARM32Ldr(Cfg *Func, Variable *Dest, OperandARM32Mem *Mem)
     : InstARM32(Func, InstARM32::Ldr, 1, Dest) {
   addSource(Mem);
 }
 
+InstARM32Mla::InstARM32Mla(Cfg *Func, Variable *Dest, Variable *Src0,
+                           Variable *Src1, Variable *Acc)
+    : InstARM32(Func, InstARM32::Mla, 3, Dest) {
+  addSource(Src0);
+  addSource(Src1);
+  addSource(Acc);
+}
+
 InstARM32Ret::InstARM32Ret(Cfg *Func, Variable *LR, Variable *Source)
     : InstARM32(Func, InstARM32::Ret, Source ? 2 : 1, nullptr) {
   addSource(LR);
   if (Source)
     addSource(Source);
 }
 
+InstARM32Umull::InstARM32Umull(Cfg *Func, Variable *DestLo, Variable *DestHi,
+                               Variable *Src0, Variable *Src1)
+    : InstARM32(Func, InstARM32::Umull, 2, DestLo),
+      // DestHi is expected to have a FakeDef inserted by the lowering code.
+      DestHi(DestHi) {
+  addSource(Src0);
+  addSource(Src1);
+}
+
 // ======================== Dump routines ======================== //
 
 // Two-addr ops
 template <> const char *InstARM32Movt::Opcode = "movt";
 // Unary ops
 template <> const char *InstARM32Movw::Opcode = "movw";
 template <> const char *InstARM32Mvn::Opcode = "mvn";
 // Mov-like ops
 template <> const char *InstARM32Mov::Opcode = "mov";
+// Three-addr ops
+template <> const char *InstARM32Adc::Opcode = "adc";
+template <> const char *InstARM32Add::Opcode = "add";
+template <> const char *InstARM32And::Opcode = "and";
+template <> const char *InstARM32Eor::Opcode = "eor";
+template <> const char *InstARM32Mul::Opcode = "mul";
+template <> const char *InstARM32Orr::Opcode = "orr";
+template <> const char *InstARM32Sbc::Opcode = "sbc";
+template <> const char *InstARM32Sub::Opcode = "sub";
 
 void InstARM32::dump(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "[ARM32] ";
   Inst::dump(Func);
 }
 
 template <> void InstARM32Mov::emit(const Cfg *Func) const {
@@ skipping 35 matching lines @@
   assert(getDest()->hasReg());
   Type Ty = getSrc(0)->getType();
   Str << "\t"
       << "ldr" << getWidthString(Ty) << "\t";
   getDest()->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 void InstARM32Ldr::emitIAS(const Cfg *Func) const {
-  assert(getSrcSize() == 2);
+  assert(getSrcSize() == 1);
   (void)Func;
   llvm_unreachable("Not yet implemented");
 }
 
 void InstARM32Ldr::dump(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
-  Str << "ldr." << getSrc(0)->getType() << " ";
+  Str << " = ldr." << getSrc(0)->getType() << " ";
   dumpSources(Func);
 }
 
+void InstARM32Mla::emit(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 3);
+  assert(getDest()->hasReg());
+  Str << "\t"
+      << "mla"
+      << "\t";
+  getDest()->emit(Func);
+  Str << ", ";
+  getSrc(0)->emit(Func);
+  Str << ", ";
+  getSrc(1)->emit(Func);
+  Str << ", ";
+  getSrc(2)->emit(Func);
+}
+
+void InstARM32Mla::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 3);
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
+void InstARM32Mla::dump(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  dumpDest(Func);
+  Str << " = mla." << getSrc(0)->getType() << " ";
+  dumpSources(Func);
+}
+
 template <> void InstARM32Movw::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Str << "\t" << Opcode << "\t";
   getDest()->emit(Func);
   Str << ", ";
   Constant *Src0 = llvm::cast<Constant>(getSrc(0));
   if (auto CR = llvm::dyn_cast<ConstantRelocatable>(Src0)) {
@@ skipping 23 matching lines @@
 }
 
 void InstARM32Ret::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   assert(getSrcSize() > 0);
   Variable *LR = llvm::cast<Variable>(getSrc(0));
   assert(LR->hasReg());
   assert(LR->getRegNum() == RegARM32::Reg_lr);
   Ostream &Str = Func->getContext()->getStrEmit();
-  Str << "\tbx\t";
+  Str << "\t"
+      << "bx"
+      << "\t";
   LR->emit(Func);
 }
 
 void InstARM32Ret::emitIAS(const Cfg *Func) const {
   (void)Func;
   llvm_unreachable("Not yet implemented");
 }
 
 void InstARM32Ret::dump(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Type Ty = (getSrcSize() == 1 ? IceType_void : getSrc(0)->getType());
   Str << "ret." << Ty << " ";
   dumpSources(Func);
 }
 
+void InstARM32Umull::emit(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 2);
+  assert(getDest()->hasReg());
+  Str << "\t"
+      << "umull"
+      << "\t";
+  getDest()->emit(Func);
+  Str << ", ";
+  DestHi->emit(Func);
+  Str << ", ";
+  getSrc(0)->emit(Func);
+  Str << ", ";
+  getSrc(1)->emit(Func);
+}
+
+void InstARM32Umull::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 2);
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
+void InstARM32Umull::dump(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  dumpDest(Func);
+  Str << " = umull." << getSrc(0)->getType() << " ";
+  dumpSources(Func);
+}
+
 void OperandARM32Mem::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "[";
   getBase()->emit(Func);
   switch (getAddrMode()) {
   case PostIndex:
   case NegPostIndex:
     Str << "], ";
@@ skipping 96 matching lines @@
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     if (Func)
       getShiftAmt()->dump(Func);
     else
       getShiftAmt()->dump(Str);
   }
 }
 
 } // end of namespace Ice