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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file declares the TargetLoweringARM32 class, which implements the | 10 // This file declares the TargetLoweringARM32 class, which implements the |
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123 Variable *makeVectorOfZeros(Type Ty, int32_t RegNum = Variable::NoRegister); | 123 Variable *makeVectorOfZeros(Type Ty, int32_t RegNum = Variable::NoRegister); |
124 | 124 |
125 void makeRandomRegisterPermutation( | 125 void makeRandomRegisterPermutation( |
126 llvm::SmallVectorImpl<int32_t> &Permutation, | 126 llvm::SmallVectorImpl<int32_t> &Permutation, |
127 const llvm::SmallBitVector &ExcludeRegisters) const override; | 127 const llvm::SmallBitVector &ExcludeRegisters) const override; |
128 | 128 |
129 // The following are helpers that insert lowered ARM32 instructions | 129 // The following are helpers that insert lowered ARM32 instructions |
130 // with minimal syntactic overhead, so that the lowering code can | 130 // with minimal syntactic overhead, so that the lowering code can |
131 // look as close to assembly as practical. | 131 // look as close to assembly as practical. |
132 | 132 |
| 133 void _add(Variable *Dest, Variable *Src0, Operand *Src1) { |
| 134 Context.insert(InstARM32Add::create(Func, Dest, Src0, Src1)); |
| 135 } |
| 136 void _adds(Variable *Dest, Variable *Src0, Operand *Src1) { |
| 137 const bool SetFlags = true; |
| 138 Context.insert(InstARM32Add::create(Func, Dest, Src0, Src1, SetFlags)); |
| 139 } |
| 140 void _adc(Variable *Dest, Variable *Src0, Operand *Src1) { |
| 141 Context.insert(InstARM32Adc::create(Func, Dest, Src0, Src1)); |
| 142 } |
| 143 void _and(Variable *Dest, Variable *Src0, Operand *Src1) { |
| 144 Context.insert(InstARM32And::create(Func, Dest, Src0, Src1)); |
| 145 } |
| 146 void _eor(Variable *Dest, Variable *Src0, Operand *Src1) { |
| 147 Context.insert(InstARM32Eor::create(Func, Dest, Src0, Src1)); |
| 148 } |
133 void _ldr(Variable *Dest, OperandARM32Mem *Addr) { | 149 void _ldr(Variable *Dest, OperandARM32Mem *Addr) { |
134 Context.insert(InstARM32Ldr::create(Func, Dest, Addr)); | 150 Context.insert(InstARM32Ldr::create(Func, Dest, Addr)); |
135 } | 151 } |
| 152 void _mla(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc) { |
| 153 Context.insert(InstARM32Mla::create(Func, Dest, Src0, Src1, Acc)); |
| 154 } |
136 // If Dest=nullptr is passed in, then a new variable is created, | 155 // If Dest=nullptr is passed in, then a new variable is created, |
137 // marked as infinite register allocation weight, and returned | 156 // marked as infinite register allocation weight, and returned |
138 // through the in/out Dest argument. | 157 // through the in/out Dest argument. |
139 void _mov(Variable *&Dest, Operand *Src0, | 158 void _mov(Variable *&Dest, Operand *Src0, |
140 int32_t RegNum = Variable::NoRegister) { | 159 int32_t RegNum = Variable::NoRegister) { |
141 if (Dest == nullptr) | 160 if (Dest == nullptr) |
142 Dest = makeReg(Src0->getType(), RegNum); | 161 Dest = makeReg(Src0->getType(), RegNum); |
143 Context.insert(InstARM32Mov::create(Func, Dest, Src0)); | 162 Context.insert(InstARM32Mov::create(Func, Dest, Src0)); |
144 } | 163 } |
145 // The Operand can only be a 16-bit immediate or a ConstantRelocatable | 164 // The Operand can only be a 16-bit immediate or a ConstantRelocatable |
146 // (with an upper16 relocation). | 165 // (with an upper16 relocation). |
147 void _movt(Variable *&Dest, Operand *Src0) { | 166 void _movt(Variable *Dest, Operand *Src0) { |
148 Context.insert(InstARM32Movt::create(Func, Dest, Src0)); | 167 Context.insert(InstARM32Movt::create(Func, Dest, Src0)); |
149 } | 168 } |
150 void _movw(Variable *&Dest, Operand *Src0) { | 169 void _movw(Variable *Dest, Operand *Src0) { |
151 Context.insert(InstARM32Movw::create(Func, Dest, Src0)); | 170 Context.insert(InstARM32Movw::create(Func, Dest, Src0)); |
152 } | 171 } |
153 void _mvn(Variable *&Dest, Operand *Src0) { | 172 void _mul(Variable *Dest, Variable *Src0, Variable *Src1) { |
| 173 Context.insert(InstARM32Mul::create(Func, Dest, Src0, Src1)); |
| 174 } |
| 175 void _mvn(Variable *Dest, Operand *Src0) { |
154 Context.insert(InstARM32Mvn::create(Func, Dest, Src0)); | 176 Context.insert(InstARM32Mvn::create(Func, Dest, Src0)); |
155 } | 177 } |
| 178 void _orr(Variable *Dest, Variable *Src0, Operand *Src1) { |
| 179 Context.insert(InstARM32Orr::create(Func, Dest, Src0, Src1)); |
| 180 } |
| 181 void _sbc(Variable *Dest, Variable *Src0, Operand *Src1) { |
| 182 Context.insert(InstARM32Sbc::create(Func, Dest, Src0, Src1)); |
| 183 } |
| 184 void _sub(Variable *Dest, Variable *Src0, Operand *Src1) { |
| 185 Context.insert(InstARM32Sub::create(Func, Dest, Src0, Src1)); |
| 186 } |
| 187 void _subs(Variable *Dest, Variable *Src0, Operand *Src1) { |
| 188 const bool SetFlags = true; |
| 189 Context.insert(InstARM32Sub::create(Func, Dest, Src0, Src1, SetFlags)); |
| 190 } |
156 void _ret(Variable *LR, Variable *Src0 = nullptr) { | 191 void _ret(Variable *LR, Variable *Src0 = nullptr) { |
157 Context.insert(InstARM32Ret::create(Func, LR, Src0)); | 192 Context.insert(InstARM32Ret::create(Func, LR, Src0)); |
158 } | 193 } |
| 194 void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0, |
| 195 Variable *Src1) { |
| 196 Context.insert(InstARM32Umull::create(Func, DestLo, DestHi, Src0, Src1)); |
| 197 // Model the modification to the second dest as a fake def. |
| 198 Context.insert(InstFakeDef::create(Func, DestHi, DestLo)); |
| 199 } |
159 | 200 |
160 bool UsesFramePointer; | 201 bool UsesFramePointer; |
161 bool NeedsStackAlignment; | 202 bool NeedsStackAlignment; |
162 llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; | 203 llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; |
163 llvm::SmallBitVector ScratchRegs; | 204 llvm::SmallBitVector ScratchRegs; |
164 llvm::SmallBitVector RegsUsed; | 205 llvm::SmallBitVector RegsUsed; |
165 VarList PhysicalRegisters[IceType_NUM]; | 206 VarList PhysicalRegisters[IceType_NUM]; |
166 static IceString RegNames[]; | 207 static IceString RegNames[]; |
167 | 208 |
168 private: | 209 private: |
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187 | 228 |
188 private: | 229 private: |
189 void lowerGlobal(const VariableDeclaration &Var) const; | 230 void lowerGlobal(const VariableDeclaration &Var) const; |
190 ~TargetDataARM32() override {} | 231 ~TargetDataARM32() override {} |
191 template <typename T> static void emitConstantPool(GlobalContext *Ctx); | 232 template <typename T> static void emitConstantPool(GlobalContext *Ctx); |
192 }; | 233 }; |
193 | 234 |
194 } // end of namespace Ice | 235 } // end of namespace Ice |
195 | 236 |
196 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 237 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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