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Side by Side Diff: runtime/vm/assembler_arm64.h

Issue 1124173002: Implement Smi_bitLength intrinsic on mips, arm, and arm64. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 5 years, 7 months ago
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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_ASSEMBLER_ARM64_H_ 5 #ifndef VM_ASSEMBLER_ARM64_H_
6 #define VM_ASSEMBLER_ARM64_H_ 6 #define VM_ASSEMBLER_ARM64_H_
7 7
8 #ifndef VM_ASSEMBLER_H_ 8 #ifndef VM_ASSEMBLER_H_
9 #error Do not include assembler_arm64.h directly; use assembler.h instead. 9 #error Do not include assembler_arm64.h directly; use assembler.h instead.
10 #endif 10 #endif
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653 void eon(Register rd, Register rn, Operand o) { 653 void eon(Register rd, Register rn, Operand o) {
654 EmitLogicalShiftOp(EON, rd, rn, o, kDoubleWord); 654 EmitLogicalShiftOp(EON, rd, rn, o, kDoubleWord);
655 } 655 }
656 void ands(Register rd, Register rn, Operand o) { 656 void ands(Register rd, Register rn, Operand o) {
657 EmitLogicalShiftOp(ANDS, rd, rn, o, kDoubleWord); 657 EmitLogicalShiftOp(ANDS, rd, rn, o, kDoubleWord);
658 } 658 }
659 void bics(Register rd, Register rn, Operand o) { 659 void bics(Register rd, Register rn, Operand o) {
660 EmitLogicalShiftOp(BICS, rd, rn, o, kDoubleWord); 660 EmitLogicalShiftOp(BICS, rd, rn, o, kDoubleWord);
661 } 661 }
662 662
663 // Count leading zero bits.
664 void clz(Register rd, Register rn) {
665 EmitMiscDP1Source(CLZ, rd, rn, kDoubleWord);
666 }
667
663 // Misc. arithmetic. 668 // Misc. arithmetic.
664 void udiv(Register rd, Register rn, Register rm) { 669 void udiv(Register rd, Register rn, Register rm) {
665 EmitMiscDP2Source(UDIV, rd, rn, rm, kDoubleWord); 670 EmitMiscDP2Source(UDIV, rd, rn, rm, kDoubleWord);
666 } 671 }
667 void sdiv(Register rd, Register rn, Register rm) { 672 void sdiv(Register rd, Register rn, Register rm) {
668 EmitMiscDP2Source(SDIV, rd, rn, rm, kDoubleWord); 673 EmitMiscDP2Source(SDIV, rd, rn, rm, kDoubleWord);
669 } 674 }
670 void lslv(Register rd, Register rn, Register rm) { 675 void lslv(Register rd, Register rn, Register rm) {
671 EmitMiscDP2Source(LSLV, rd, rn, rm, kDoubleWord); 676 EmitMiscDP2Source(LSLV, rd, rn, rm, kDoubleWord);
672 } 677 }
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1775 ASSERT((rd != R31) && (rd != CSP)); 1780 ASSERT((rd != R31) && (rd != CSP));
1776 const Register crd = ConcreteRegister(rd); 1781 const Register crd = ConcreteRegister(rd);
1777 const int32_t loimm = (imm.value() & 0x3) << 29; 1782 const int32_t loimm = (imm.value() & 0x3) << 29;
1778 const int32_t hiimm = ((imm.value() >> 2) << kImm19Shift) & kImm19Mask; 1783 const int32_t hiimm = ((imm.value() >> 2) << kImm19Shift) & kImm19Mask;
1779 const int32_t encoding = 1784 const int32_t encoding =
1780 op | loimm | hiimm | 1785 op | loimm | hiimm |
1781 (static_cast<int32_t>(crd) << kRdShift); 1786 (static_cast<int32_t>(crd) << kRdShift);
1782 Emit(encoding); 1787 Emit(encoding);
1783 } 1788 }
1784 1789
1790 void EmitMiscDP1Source(MiscDP1SourceOp op,
1791 Register rd, Register rn,
1792 OperandSize sz) {
1793 ASSERT((rd != CSP) && (rn != CSP));
1794 ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
1795 const Register crd = ConcreteRegister(rd);
1796 const Register crn = ConcreteRegister(rn);
1797 const int32_t size = (sz == kDoubleWord) ? B31 : 0;
1798 const int32_t encoding =
1799 op | size |
1800 (static_cast<int32_t>(crd) << kRdShift) |
1801 (static_cast<int32_t>(crn) << kRnShift);
1802 Emit(encoding);
1803 }
1804
1785 void EmitMiscDP2Source(MiscDP2SourceOp op, 1805 void EmitMiscDP2Source(MiscDP2SourceOp op,
1786 Register rd, Register rn, Register rm, 1806 Register rd, Register rn, Register rm,
1787 OperandSize sz) { 1807 OperandSize sz) {
1788 ASSERT((rd != CSP) && (rn != CSP) && (rm != CSP)); 1808 ASSERT((rd != CSP) && (rn != CSP) && (rm != CSP));
1789 ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord)); 1809 ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
1790 const Register crd = ConcreteRegister(rd); 1810 const Register crd = ConcreteRegister(rd);
1791 const Register crn = ConcreteRegister(rn); 1811 const Register crn = ConcreteRegister(rn);
1792 const Register crm = ConcreteRegister(rm); 1812 const Register crm = ConcreteRegister(rm);
1793 const int32_t size = (sz == kDoubleWord) ? B31 : 0; 1813 const int32_t size = (sz == kDoubleWord) ? B31 : 0;
1794 const int32_t encoding = 1814 const int32_t encoding =
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1921 Register value, 1941 Register value,
1922 Label* no_update); 1942 Label* no_update);
1923 1943
1924 DISALLOW_ALLOCATION(); 1944 DISALLOW_ALLOCATION();
1925 DISALLOW_COPY_AND_ASSIGN(Assembler); 1945 DISALLOW_COPY_AND_ASSIGN(Assembler);
1926 }; 1946 };
1927 1947
1928 } // namespace dart 1948 } // namespace dart
1929 1949
1930 #endif // VM_ASSEMBLER_ARM64_H_ 1950 #endif // VM_ASSEMBLER_ARM64_H_
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