Change BKPT and UDF encodings on ARM.

src/trusted/validator_arm/gen/arm32_decode.cc

 /*
  * Copyright 2012 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 
 #include "native_client/src/trusted/validator_arm/gen/arm32_decode.h"
@@ skipping 33 matching lines @@
   , LoadBasedOffsetMemory_instance_()
   , LoadBasedOffsetMemoryDouble_instance_()
   , LoadMultiple_instance_()
   , LoadVectorRegister_instance_()
   , LoadVectorRegisterList_instance_()
   , MaskAddress_instance_()
   , MoveDoubleVfpRegisterOp_instance_()
   , MoveVfpRegisterOp_instance_()
   , MoveVfpRegisterOpWithTypeSel_instance_()
   , NotImplemented_instance_()
+  , PermanentlyUndefined_instance_()
   , PreloadRegisterPairOp_instance_()
   , PreloadRegisterPairOpWAndRnNotPc_instance_()
-  , Roadblock_instance_()
   , Store2RegisterImm12OpRnNotRtOnWriteback_instance_()
   , StoreBasedImmedMemory_instance_()
   , StoreBasedImmedMemoryDouble_instance_()
   , StoreBasedMemoryDoubleRtBits0To3_instance_()
   , StoreBasedMemoryRtBits0To3_instance_()
   , StoreBasedOffsetMemory_instance_()
   , StoreBasedOffsetMemoryDouble_instance_()
   , StoreRegisterList_instance_()
   , StoreVectorRegister_instance_()
   , StoreVectorRegisterList_instance_()
@@ skipping 794 matching lines @@
   }
 
   if ((inst.Bits() & 0x01F00000) == 0x01800000 /* op1(24:20)=11000 */ &&
       (inst.Bits() & 0x000000E0) == 0x00000000 /* op2(7:5)=000 */ &&
       (inst.Bits() & 0x0000F000) == 0x0000F000 /* Rd(15:12)=1111 */) {
     return Defs16To19CondsDontCareRdRmRnNotPc_instance_;
   }
 
   if ((inst.Bits() & 0x01F00000) == 0x01F00000 /* op1(24:20)=11111 */ &&
       (inst.Bits() & 0x000000E0) == 0x000000E0 /* op2(7:5)=111 */) {
-    return Roadblock_instance_;
+    return PermanentlyUndefined_instance_;
   }
 
   if ((inst.Bits() & 0x01E00000) == 0x01C00000 /* op1(24:20)=1110x */ &&
       (inst.Bits() & 0x00000060) == 0x00000000 /* op2(7:5)=x00 */ &&
       (inst.Bits() & 0x0000000F) != 0x0000000F /* Rn(3:0)=~1111 */) {
     return Defs12To15CondsDontCareMsbGeLsb_instance_;
   }
 
   if ((inst.Bits() & 0x01E00000) == 0x01C00000 /* op1(24:20)=1110x */ &&
       (inst.Bits() & 0x00000060) == 0x00000000 /* op2(7:5)=x00 */ &&
@@ skipping 1326 matching lines @@
 
   // Catch any attempt to fall though ...
   return not_implemented_;
 }
 
 const ClassDecoder& Arm32DecoderState::decode(const Instruction inst) const {
   return decode_ARMv7(inst);
 }
 
 }  // namespace nacl_arm_dec