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1 # ARMv7 Instruction Encodings | 1 # ARMv7 Instruction Encodings |
2 # | 2 # |
3 # This table is derived from the "ARM Architecture Reference Manual, ARMv7-A | 3 # This table is derived from the "ARM Architecture Reference Manual, ARMv7-A |
4 # and ARMv7-R edition" and is used here with the permission of ARM Limited. | 4 # and ARMv7-R edition" and is used here with the permission of ARM Limited. |
5 # Reproduction for purposes other than the development and distribution of | 5 # Reproduction for purposes other than the development and distribution of |
6 # Native Client may require the explicit permission of ARM Limited. | 6 # Native Client may require the explicit permission of ARM Limited. |
7 | 7 |
8 # This file defines the Native Client "instruction classes" assigned to every | 8 # This file defines the Native Client "instruction classes" assigned to every |
9 # possible ARMv7 instruction encoding. It is organized into a series of tables, | 9 # possible ARMv7 instruction encoding. It is organized into a series of tables, |
10 # and directly parallels the ARM Architecture Reference Manual cited above. | 10 # and directly parallels the ARM Architecture Reference Manual cited above. |
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1034 | " " - ~1111 = Binary2RegisterBitRangeMsbGeLsb | 1034 | " " - ~1111 = Binary2RegisterBitRangeMsbGeLsb |
1035 => Defs12To15CondsDontCareMsbGeLsb | 1035 => Defs12To15CondsDontCareMsbGeLsb |
1036 Bfi_Rule_18_A1_P48 | 1036 Bfi_Rule_18_A1_P48 |
1037 cccc0111110mmmmmddddlllll001nnnn | 1037 cccc0111110mmmmmddddlllll001nnnn |
1038 RegsNotPc (v6T2) | 1038 RegsNotPc (v6T2) |
1039 | 1111x x10 - - = Binary2RegisterBitRangeNotRnIsPcBitfield
Extract | 1039 | 1111x x10 - - = Binary2RegisterBitRangeNotRnIsPcBitfield
Extract |
1040 => Defs12To15CondsDontCareRdRnNotPcBitfi
eldExtract | 1040 => Defs12To15CondsDontCareRdRnNotPcBitfi
eldExtract |
1041 Ubfx_Rule_236_A1_P466 | 1041 Ubfx_Rule_236_A1_P466 |
1042 cccc0111111mmmmmddddlllll101nnnn | 1042 cccc0111111mmmmmddddlllll101nnnn |
1043 RegsNotPc (v6T2) | 1043 RegsNotPc (v6T2) |
1044 | 11111 111 - - = Roadblock # Permanently Undefined | 1044 | 11111 111 - - = PermanentlyUndefined |
1045 # Note: the UDF mnemonic only applies | 1045 # Note: the UDF mnemonic only applies |
1046 # when cond == 0b1110, but all | 1046 # when cond == 0b1110, but all |
1047 # encodings are permanently undefined. | 1047 # encodings are permanently undefined. |
1048 Udf_Rule_A1 | 1048 Udf_Rule_A1 |
1049 cccc01111111iiiiiiiiiiii1111iiii | 1049 cccc01111111iiiiiiiiiiii1111iiii |
1050 | else: = Undefined # Note on page A5-21 | 1050 | else: = Undefined # Note on page A5-21 |
1051 +-- | 1051 +-- |
1052 | 1052 |
1053 # None of the instructions in the following table set NZCV flags. | 1053 # None of the instructions in the following table set NZCV flags. |
1054 # Some do set the APSR's sticky Q bit (for saturation) or the GE bits, | 1054 # Some do set the APSR's sticky Q bit (for saturation) or the GE bits, |
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2687 | " 1001 " | 2687 | " 1001 " |
2688 | " 1101 =VectorLoad # VLD2(single, all lanes) | 2688 | " 1101 =VectorLoad # VLD2(single, all lanes) |
2689 | " 0x10 =VectorLoad # VLD3(single) | 2689 | " 0x10 =VectorLoad # VLD3(single) |
2690 | " 1010 " | 2690 | " 1010 " |
2691 | " 1110 =VectorLoad # VLD3(single, all lanes) | 2691 | " 1110 =VectorLoad # VLD3(single, all lanes) |
2692 | " 0x11 =VectorLoad # VLD4(single) | 2692 | " 0x11 =VectorLoad # VLD4(single) |
2693 | " 1011 " | 2693 | " 1011 " |
2694 | " 1111 =VectorLoad # VLD4(single, all lanes) | 2694 | " 1111 =VectorLoad # VLD4(single, all lanes) |
2695 | else: =Undefined # Note on page A7-27 | 2695 | else: =Undefined # Note on page A7-27 |
2696 +-- | 2696 +-- |
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