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| 1 /* | 1 /* | 
| 2  * Copyright (c) 2012 The Native Client Authors. All rights reserved. | 2  * Copyright (c) 2012 The Native Client Authors. All rights reserved. | 
| 3  * Use of this source code is governed by a BSD-style license that can be | 3  * Use of this source code is governed by a BSD-style license that can be | 
| 4  * found in the LICENSE file. | 4  * found in the LICENSE file. | 
| 5  */ | 5  */ | 
| 6 | 6 | 
| 7 #ifndef NACL_TRUSTED_BUT_NOT_TCB | 7 #ifndef NACL_TRUSTED_BUT_NOT_TCB | 
| 8 #error This file is not meant for use in the TCB | 8 #error This file is not meant for use in the TCB | 
| 9 #endif | 9 #endif | 
| 10 | 10 | 
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| 99         // cccc 0001 0010 1111 1111 1111 00L1 mmmm | 99         // cccc 0001 0010 1111 1111 1111 00L1 mmmm | 
| 100         ((i & 0x0FFFFFD0) == 0x012FFF10); | 100         ((i & 0x0FFFFFD0) == 0x012FFF10); | 
| 101     uint32_t expected_branch_target = !expect_b_or_bl ? | 101     uint32_t expected_branch_target = !expect_b_or_bl ? | 
| 102         kDefaultBaseAddr : | 102         kDefaultBaseAddr : | 
| 103         // imm32 = SignExtend(imm24:'00', 32); | 103         // imm32 = SignExtend(imm24:'00', 32); | 
| 104         // PC reads as the address of the current instruction plus 8. | 104         // PC reads as the address of the current instruction plus 8. | 
| 105         (kDefaultBaseAddr + 8 + (((int32_t)i << 8) >> 6)); | 105         (kDefaultBaseAddr + 8 + (((int32_t)i << 8) >> 6)); | 
| 106     uint32_t expected_branch_target_register = expect_bx_or_blx ? | 106     uint32_t expected_branch_target_register = expect_bx_or_blx ? | 
| 107         (i & 0xF) :  // When present, always Rm(3:0). | 107         (i & 0xF) :  // When present, always Rm(3:0). | 
| 108         nacl_arm_dec::Register::kNone; | 108         nacl_arm_dec::Register::kNone; | 
| 109     bool expect_literal_pool_head = | 109     bool expect_literal_pool_head =(i == nacl_arm_dec::kLiteralPoolHead); | 
| 110         (i == nacl_arm_dec::kLiteralPoolHeadInstruction); |  | 
| 111     bool expect_load_store_or_unsafe = expect_unconditional ? | 110     bool expect_load_store_or_unsafe = expect_unconditional ? | 
| 112         // Advanced SIMD element or structure load/store instructions. | 111         // Advanced SIMD element or structure load/store instructions. | 
| 113         // 1111 0100 xx0x xxxx xxxx xxxx xxxx xxxx | 112         // 1111 0100 xx0x xxxx xxxx xxxx xxxx xxxx | 
| 114         ((i & 0x0F100000) == 0x04000000) : | 113         ((i & 0x0F100000) == 0x04000000) : | 
| 115         (  // Conditional instructions: | 114         (  // Conditional instructions: | 
| 116             // Synchronization primitives. | 115             // Synchronization primitives. | 
| 117             // cccc 0001 xxxx xxxx xxxx xxxx 1001 xxxx | 116             // cccc 0001 xxxx xxxx xxxx xxxx 1001 xxxx | 
| 118             ((i & 0x0F0000F0) == 0x01000090) || | 117             ((i & 0x0F0000F0) == 0x01000090) || | 
| 119             // Extra load/store instructions[, unprivileged]. | 118             // Extra load/store instructions[, unprivileged]. | 
| 120             // cccc 000x xxxx xxxx xxxx xxxx 1011 xxxx | 119             // cccc 000x xxxx xxxx xxxx xxxx 1011 xxxx | 
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| 248   } while (i++ != last_i); | 247   } while (i++ != last_i); | 
| 249 } | 248 } | 
| 250 | 249 | 
| 251 }  // anonymous namespace | 250 }  // anonymous namespace | 
| 252 | 251 | 
| 253 // Test driver function. | 252 // Test driver function. | 
| 254 int main(int argc, char *argv[]) { | 253 int main(int argc, char *argv[]) { | 
| 255   testing::InitGoogleTest(&argc, argv); | 254   testing::InitGoogleTest(&argc, argv); | 
| 256   return RUN_ALL_TESTS(); | 255   return RUN_ALL_TESTS(); | 
| 257 } | 256 } | 
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