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Side by Side Diff: src/trusted/validator_arm/gen/arm32_decode.h

Issue 11194045: Change BKPT and UDF encodings on ARM. (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client
Patch Set: Clarify comments. Fix unaligned_data_irt.nexe, it had a hard-coded BKPT #0x7777. Created 8 years, 2 months ago
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1 /* 1 /*
2 * Copyright 2012 The Native Client Authors. All rights reserved. 2 * Copyright 2012 The Native Client Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can 3 * Use of this source code is governed by a BSD-style license that can
4 * be found in the LICENSE file. 4 * be found in the LICENSE file.
5 */ 5 */
6 6
7 // DO NOT EDIT: GENERATED CODE 7 // DO NOT EDIT: GENERATED CODE
8 8
9 9
10 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_H_ 10 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_H_
(...skipping 156 matching lines...) Expand 10 before | Expand all | Expand 10 after
167 const LoadBasedOffsetMemory LoadBasedOffsetMemory_instance_; 167 const LoadBasedOffsetMemory LoadBasedOffsetMemory_instance_;
168 const LoadBasedOffsetMemoryDouble LoadBasedOffsetMemoryDouble_instance_; 168 const LoadBasedOffsetMemoryDouble LoadBasedOffsetMemoryDouble_instance_;
169 const LoadMultiple LoadMultiple_instance_; 169 const LoadMultiple LoadMultiple_instance_;
170 const LoadVectorRegister LoadVectorRegister_instance_; 170 const LoadVectorRegister LoadVectorRegister_instance_;
171 const LoadVectorRegisterList LoadVectorRegisterList_instance_; 171 const LoadVectorRegisterList LoadVectorRegisterList_instance_;
172 const MaskAddress MaskAddress_instance_; 172 const MaskAddress MaskAddress_instance_;
173 const MoveDoubleVfpRegisterOp MoveDoubleVfpRegisterOp_instance_; 173 const MoveDoubleVfpRegisterOp MoveDoubleVfpRegisterOp_instance_;
174 const MoveVfpRegisterOp MoveVfpRegisterOp_instance_; 174 const MoveVfpRegisterOp MoveVfpRegisterOp_instance_;
175 const MoveVfpRegisterOpWithTypeSel MoveVfpRegisterOpWithTypeSel_instance_; 175 const MoveVfpRegisterOpWithTypeSel MoveVfpRegisterOpWithTypeSel_instance_;
176 const NotImplemented NotImplemented_instance_; 176 const NotImplemented NotImplemented_instance_;
177 const PermanentlyUndefined PermanentlyUndefined_instance_;
177 const PreloadRegisterPairOp PreloadRegisterPairOp_instance_; 178 const PreloadRegisterPairOp PreloadRegisterPairOp_instance_;
178 const PreloadRegisterPairOpWAndRnNotPc PreloadRegisterPairOpWAndRnNotPc_instan ce_; 179 const PreloadRegisterPairOpWAndRnNotPc PreloadRegisterPairOpWAndRnNotPc_instan ce_;
179 const Roadblock Roadblock_instance_;
180 const Store2RegisterImm12OpRnNotRtOnWriteback Store2RegisterImm12OpRnNotRtOnWr iteback_instance_; 180 const Store2RegisterImm12OpRnNotRtOnWriteback Store2RegisterImm12OpRnNotRtOnWr iteback_instance_;
181 const StoreBasedImmedMemory StoreBasedImmedMemory_instance_; 181 const StoreBasedImmedMemory StoreBasedImmedMemory_instance_;
182 const StoreBasedImmedMemoryDouble StoreBasedImmedMemoryDouble_instance_; 182 const StoreBasedImmedMemoryDouble StoreBasedImmedMemoryDouble_instance_;
183 const StoreBasedMemoryDoubleRtBits0To3 StoreBasedMemoryDoubleRtBits0To3_instan ce_; 183 const StoreBasedMemoryDoubleRtBits0To3 StoreBasedMemoryDoubleRtBits0To3_instan ce_;
184 const StoreBasedMemoryRtBits0To3 StoreBasedMemoryRtBits0To3_instance_; 184 const StoreBasedMemoryRtBits0To3 StoreBasedMemoryRtBits0To3_instance_;
185 const StoreBasedOffsetMemory StoreBasedOffsetMemory_instance_; 185 const StoreBasedOffsetMemory StoreBasedOffsetMemory_instance_;
186 const StoreBasedOffsetMemoryDouble StoreBasedOffsetMemoryDouble_instance_; 186 const StoreBasedOffsetMemoryDouble StoreBasedOffsetMemoryDouble_instance_;
187 const StoreRegisterList StoreRegisterList_instance_; 187 const StoreRegisterList StoreRegisterList_instance_;
188 const StoreVectorRegister StoreVectorRegister_instance_; 188 const StoreVectorRegister StoreVectorRegister_instance_;
189 const StoreVectorRegisterList StoreVectorRegisterList_instance_; 189 const StoreVectorRegisterList StoreVectorRegisterList_instance_;
(...skipping 22 matching lines...) Expand all
212 const VectorBinary3RegisterSameLengthDQI8P VectorBinary3RegisterSameLengthDQI8 P_instance_; 212 const VectorBinary3RegisterSameLengthDQI8P VectorBinary3RegisterSameLengthDQI8 P_instance_;
213 const VectorBinary3RegisterSameLengthDQI8_16_32 VectorBinary3RegisterSameLengt hDQI8_16_32_instance_; 213 const VectorBinary3RegisterSameLengthDQI8_16_32 VectorBinary3RegisterSameLengt hDQI8_16_32_instance_;
214 const VectorUnary2RegisterDup VectorUnary2RegisterDup_instance_; 214 const VectorUnary2RegisterDup VectorUnary2RegisterDup_instance_;
215 const VfpMrsOp VfpMrsOp_instance_; 215 const VfpMrsOp VfpMrsOp_instance_;
216 const VfpOp VfpOp_instance_; 216 const VfpOp VfpOp_instance_;
217 const NotImplemented not_implemented_; 217 const NotImplemented not_implemented_;
218 }; 218 };
219 219
220 } // namespace nacl_arm_dec 220 } // namespace nacl_arm_dec
221 #endif // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_H_ 221 #endif // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_H_
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