| OLD | NEW |
| 1 # ARMv7 Instruction Encodings | 1 # ARMv7 Instruction Encodings |
| 2 # | 2 # |
| 3 # This table is derived from the "ARM Architecture Reference Manual, ARMv7-A | 3 # This table is derived from the "ARM Architecture Reference Manual, ARMv7-A |
| 4 # and ARMv7-R edition" and is used here with the permission of ARM Limited. | 4 # and ARMv7-R edition" and is used here with the permission of ARM Limited. |
| 5 # Reproduction for purposes other than the development and distribution of | 5 # Reproduction for purposes other than the development and distribution of |
| 6 # Native Client may require the explicit permission of ARM Limited. | 6 # Native Client may require the explicit permission of ARM Limited. |
| 7 | 7 |
| 8 # This file defines the Native Client "instruction classes" assigned to every | 8 # This file defines the Native Client "instruction classes" assigned to every |
| 9 # possible ARMv7 instruction encoding. It is organized into a series of tables, | 9 # possible ARMv7 instruction encoding. It is organized into a series of tables, |
| 10 # and directly parallels the ARM Architecture Reference Manual cited above. | 10 # and directly parallels the ARM Architecture Reference Manual cited above. |
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| 1008 | " " - ~1111 = Binary2RegisterBitRangeMsbGeLsb | 1008 | " " - ~1111 = Binary2RegisterBitRangeMsbGeLsb |
| 1009 => Defs12To15CondsDontCareMsbGeLsb | 1009 => Defs12To15CondsDontCareMsbGeLsb |
| 1010 Bfi_Rule_18_A1_P48 | 1010 Bfi_Rule_18_A1_P48 |
| 1011 cccc0111110mmmmmddddlllll001nnnn | 1011 cccc0111110mmmmmddddlllll001nnnn |
| 1012 RegsNotPc (v6T2) | 1012 RegsNotPc (v6T2) |
| 1013 | 1111x x10 - - = Binary2RegisterBitRangeNotRnIsPcBitfield
Extract | 1013 | 1111x x10 - - = Binary2RegisterBitRangeNotRnIsPcBitfield
Extract |
| 1014 => Defs12To15CondsDontCareRdRnNotPcBitfi
eldExtract | 1014 => Defs12To15CondsDontCareRdRnNotPcBitfi
eldExtract |
| 1015 Ubfx_Rule_236_A1_P466 | 1015 Ubfx_Rule_236_A1_P466 |
| 1016 cccc0111111mmmmmddddlllll101nnnn | 1016 cccc0111111mmmmmddddlllll101nnnn |
| 1017 RegsNotPc (v6T2) | 1017 RegsNotPc (v6T2) |
| 1018 | 11111 111 - - = Roadblock # Permanently Undefined | 1018 | 11111 111 - - = PermanentlyUndefined |
| 1019 # Note: the UDF mnemonic only applies | 1019 # Note: the UDF mnemonic only applies |
| 1020 # when cond == 0b1110, but all | 1020 # when cond == 0b1110, but all |
| 1021 # encodings are permanently undefined. | 1021 # encodings are permanently undefined. |
| 1022 Udf_Rule_A1 | 1022 Udf_Rule_A1 |
| 1023 cccc01111111iiiiiiiiiiii1111iiii | 1023 cccc01111111iiiiiiiiiiii1111iiii |
| 1024 | else: = Undefined # Note on page A5-21 | 1024 | else: = Undefined # Note on page A5-21 |
| 1025 +-- | 1025 +-- |
| 1026 | 1026 |
| 1027 # None of the instructions in the following table set NZCV flags. | 1027 # None of the instructions in the following table set NZCV flags. |
| 1028 # Some do set the APSR's sticky Q bit (for saturation) or the GE bits, | 1028 # Some do set the APSR's sticky Q bit (for saturation) or the GE bits, |
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| 2304 | " 1001 " | 2304 | " 1001 " |
| 2305 | " 1101 =VectorLoad # VLD2(single, all lanes) | 2305 | " 1101 =VectorLoad # VLD2(single, all lanes) |
| 2306 | " 0x10 =VectorLoad # VLD3(single) | 2306 | " 0x10 =VectorLoad # VLD3(single) |
| 2307 | " 1010 " | 2307 | " 1010 " |
| 2308 | " 1110 =VectorLoad # VLD3(single, all lanes) | 2308 | " 1110 =VectorLoad # VLD3(single, all lanes) |
| 2309 | " 0x11 =VectorLoad # VLD4(single) | 2309 | " 0x11 =VectorLoad # VLD4(single) |
| 2310 | " 1011 " | 2310 | " 1011 " |
| 2311 | " 1111 =VectorLoad # VLD4(single, all lanes) | 2311 | " 1111 =VectorLoad # VLD4(single, all lanes) |
| 2312 | else: =Undefined # Note on page A7-27 | 2312 | else: =Undefined # Note on page A7-27 |
| 2313 +-- | 2313 +-- |
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