Subzero: Produce actually correct code in -asm-verbose mode.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 780 matching lines @@
 
   // Generate "push ebp; mov ebp, esp"
   if (IsEbpBasedFrame) {
     assert((RegsUsed & getRegisterSet(RegSet_FramePointer, RegSet_None))
                .count() == 0);
     PreservedRegsSizeBytes += 4;
     Variable *ebp = getPhysicalRegister(RegX8632::Reg_ebp);
     Variable *esp = getPhysicalRegister(RegX8632::Reg_esp);
     _push(ebp);
     _mov(ebp, esp);
+    // Keep ebp live for late-stage liveness analysis
+    // (e.g. asm-verbose mode).
+    Context.insert(InstFakeUse::create(Func, ebp));
   }
 
   // Align the variables area. SpillAreaPaddingBytes is the size of
   // the region after the preserved registers and before the spill
   // areas.
   uint32_t SpillAreaPaddingBytes = 0;
   if (SpillAreaAlignmentBytes) {
     assert(SpillAreaAlignmentBytes <= X86_STACK_ALIGNMENT_BYTES);
     uint32_t PaddingStart = X86_RET_IP_SIZE_BYTES + PreservedRegsSizeBytes;
     uint32_t SpillAreaStart =
@@ skipping 122 matching lines @@
   // Convert the reverse_iterator position into its corresponding
   // (forward) iterator position.
   InstList::iterator InsertPoint = RI.base();
   --InsertPoint;
   Context.init(Node);
   Context.setInsertPoint(InsertPoint);
 
   Variable *esp = getPhysicalRegister(RegX8632::Reg_esp);
   if (IsEbpBasedFrame) {
     Variable *ebp = getPhysicalRegister(RegX8632::Reg_ebp);
+    // For late-stage liveness analysis (e.g. asm-verbose mode),
+    // adding a fake use of esp before the assignment of esp=ebp keeps
+    // previous esp adjustments from being dead-code eliminated.
+    Context.insert(InstFakeUse::create(Func, esp));
     _mov(esp, ebp);
     _pop(ebp);
   } else {
     // add esp, SpillAreaSizeBytes
     if (SpillAreaSizeBytes)
       _add(esp, Ctx->getConstantInt32(SpillAreaSizeBytes));
   }
 
   // Add pop instructions for preserved registers.
   llvm::SmallBitVector CalleeSaves =
@@ skipping 3349 matching lines @@
       // TODO(stichnot): Opportunity for register randomization.
       int32_t RegNum = AvailRegsForType.find_first();
       bool IsVector = isVectorType(Dest->getType());
       bool NeedSpill = (RegNum == -1);
       if (NeedSpill) {
         // Pick some register to spill and update RegNum.
         // TODO(stichnot): Opportunity for register randomization.
         RegNum = RegsForType.find_first();
         Preg = getPhysicalRegister(RegNum, Dest->getType());
         SpillLoc = Func->makeVariable(Dest->getType());
+        // Create a fake def of the physical register to avoid
+        // liveness inconsistency problems during late-stage liveness
+        // analysis (e.g. asm-verbose mode).
+        Context.insert(InstFakeDef::create(Func, Preg));
         if (IsVector)
           _movp(SpillLoc, Preg);
         else
           _mov(SpillLoc, Preg);
       }
       assert(RegNum >= 0);
       if (llvm::isa<ConstantUndef>(Src))
         // Materialize an actual constant instead of undef.  RegNum is
         // passed in for vector types because undef vectors are
         // lowered to vector register of zeroes.
         Src =
             legalize(Src, Legal_All, IsVector ? RegNum : Variable::NoRegister);
       Variable *Tmp = makeReg(Dest->getType(), RegNum);
       if (IsVector) {
         _movp(Tmp, Src);
         _movp(Dest, Tmp);
       } else {
         _mov(Tmp, Src);
         _mov(Dest, Tmp);
       }
       if (NeedSpill) {
         // Restore the spilled register.
         if (IsVector)
           _movp(Preg, SpillLoc);
         else
           _mov(Preg, SpillLoc);
+        // Create a fake use of the physical register to keep it live
+        // for late-stage liveness analysis (e.g. asm-verbose mode).
+        Context.insert(InstFakeUse::create(Func, Preg));
       }
     }
     // Update register availability before moving to the previous
     // instruction on the Assignments list.
     if (Dest->hasReg())
       Available[Dest->getRegNum()] = true;
     if (SrcVar && SrcVar->hasReg())
       Available[SrcVar->getRegNum()] = false;
   }
 
@@ skipping 525 matching lines @@
   case FT_Asm:
   case FT_Iasm: {
     OstreamLocker L(Ctx);
     emitConstantPool<PoolTypeConverter<float>>(Ctx);
     emitConstantPool<PoolTypeConverter<double>>(Ctx);
   } break;
   }
 }
 
 } // end of namespace Ice