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1 /* | 1 /* |
2 * Copyright (c) 2010 The WebM project authors. All Rights Reserved. | 2 * Copyright (c) 2010 The WebM project authors. All Rights Reserved. |
3 * | 3 * |
4 * Use of this source code is governed by a BSD-style license | 4 * Use of this source code is governed by a BSD-style license |
5 * that can be found in the LICENSE file in the root of the source | 5 * that can be found in the LICENSE file in the root of the source |
6 * tree. An additional intellectual property rights grant can be found | 6 * tree. An additional intellectual property rights grant can be found |
7 * in the file PATENTS. All contributing project authors may | 7 * in the file PATENTS. All contributing project authors may |
8 * be found in the AUTHORS file in the root of the source tree. | 8 * be found in the AUTHORS file in the root of the source tree. |
9 */ | 9 */ |
10 | 10 |
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145 #define HAS_AVX 0x40 | 145 #define HAS_AVX 0x40 |
146 #define HAS_AVX2 0x80 | 146 #define HAS_AVX2 0x80 |
147 #ifndef BIT | 147 #ifndef BIT |
148 #define BIT(n) (1<<n) | 148 #define BIT(n) (1<<n) |
149 #endif | 149 #endif |
150 | 150 |
151 static INLINE int | 151 static INLINE int |
152 x86_simd_caps(void) { | 152 x86_simd_caps(void) { |
153 unsigned int flags = 0; | 153 unsigned int flags = 0; |
154 unsigned int mask = ~0; | 154 unsigned int mask = ~0; |
155 unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx; | 155 unsigned int max_cpuid_val, reg_eax, reg_ebx, reg_ecx, reg_edx; |
156 char *env; | 156 char *env; |
157 (void)reg_ebx; | 157 (void)reg_ebx; |
158 | 158 |
159 /* See if the CPU capabilities are being overridden by the environment */ | 159 /* See if the CPU capabilities are being overridden by the environment */ |
160 env = getenv("VPX_SIMD_CAPS"); | 160 env = getenv("VPX_SIMD_CAPS"); |
161 | 161 |
162 if (env && *env) | 162 if (env && *env) |
163 return (int)strtol(env, NULL, 0); | 163 return (int)strtol(env, NULL, 0); |
164 | 164 |
165 env = getenv("VPX_SIMD_CAPS_MASK"); | 165 env = getenv("VPX_SIMD_CAPS_MASK"); |
166 | 166 |
167 if (env && *env) | 167 if (env && *env) |
168 mask = strtol(env, NULL, 0); | 168 mask = strtol(env, NULL, 0); |
169 | 169 |
170 /* Ensure that the CPUID instruction supports extended features */ | 170 /* Ensure that the CPUID instruction supports extended features */ |
171 cpuid(0, 0, reg_eax, reg_ebx, reg_ecx, reg_edx); | 171 cpuid(0, 0, max_cpuid_val, reg_ebx, reg_ecx, reg_edx); |
172 | 172 |
173 if (reg_eax < 1) | 173 if (max_cpuid_val < 1) |
174 return 0; | 174 return 0; |
175 | 175 |
176 /* Get the standard feature flags */ | 176 /* Get the standard feature flags */ |
177 cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx); | 177 cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx); |
178 | 178 |
179 if (reg_edx & BIT(23)) flags |= HAS_MMX; | 179 if (reg_edx & BIT(23)) flags |= HAS_MMX; |
180 | 180 |
181 if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */ | 181 if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */ |
182 | 182 |
183 if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */ | 183 if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */ |
184 | 184 |
185 if (reg_ecx & BIT(0)) flags |= HAS_SSE3; | 185 if (reg_ecx & BIT(0)) flags |= HAS_SSE3; |
186 | 186 |
187 if (reg_ecx & BIT(9)) flags |= HAS_SSSE3; | 187 if (reg_ecx & BIT(9)) flags |= HAS_SSSE3; |
188 | 188 |
189 if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1; | 189 if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1; |
190 | 190 |
191 // bits 27 (OSXSAVE) & 28 (256-bit AVX) | 191 // bits 27 (OSXSAVE) & 28 (256-bit AVX) |
192 if ((reg_ecx & (BIT(27) | BIT(28))) == (BIT(27) | BIT(28))) { | 192 if ((reg_ecx & (BIT(27) | BIT(28))) == (BIT(27) | BIT(28))) { |
193 if ((xgetbv() & 0x6) == 0x6) { | 193 if ((xgetbv() & 0x6) == 0x6) { |
194 flags |= HAS_AVX; | 194 flags |= HAS_AVX; |
195 | 195 |
196 /* Get the leaf 7 feature flags. Needed to check for AVX2 support */ | 196 if (max_cpuid_val >= 7) { |
197 cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx); | 197 /* Get the leaf 7 feature flags. Needed to check for AVX2 support */ |
| 198 cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx); |
198 | 199 |
199 if (reg_ebx & BIT(5)) flags |= HAS_AVX2; | 200 if (reg_ebx & BIT(5)) flags |= HAS_AVX2; |
| 201 } |
200 } | 202 } |
201 } | 203 } |
202 | 204 |
203 return flags & mask; | 205 return flags & mask; |
204 } | 206 } |
205 | 207 |
206 #if ARCH_X86_64 && defined(_MSC_VER) | 208 #if ARCH_X86_64 && defined(_MSC_VER) |
207 unsigned __int64 __rdtsc(void); | 209 unsigned __int64 __rdtsc(void); |
208 #pragma intrinsic(__rdtsc) | 210 #pragma intrinsic(__rdtsc) |
209 #endif | 211 #endif |
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292 } | 294 } |
293 | 295 |
294 | 296 |
295 extern void vpx_reset_mmx_state(void); | 297 extern void vpx_reset_mmx_state(void); |
296 | 298 |
297 #ifdef __cplusplus | 299 #ifdef __cplusplus |
298 } // extern "C" | 300 } // extern "C" |
299 #endif | 301 #endif |
300 | 302 |
301 #endif // VPX_PORTS_X86_H_ | 303 #endif // VPX_PORTS_X86_H_ |
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