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Issue 11037023: Use movw/movt instead of constant pool on ARMv7 (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Fix nits Created 8 years, 2 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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405 } \ 405 } \
406 void operator delete(void* object) { \ 406 void operator delete(void* object) { \
407 Logger::DeleteEventStatic(name, object); \ 407 Logger::DeleteEventStatic(name, object); \
408 ::operator delete(object); \ 408 ::operator delete(object); \
409 } 409 }
410 #else 410 #else
411 #define TRACK_MEMORY(name) 411 #define TRACK_MEMORY(name)
412 #endif 412 #endif
413 413
414 414
415 enum CpuImplementer {
416 UNKNOWN_IMPLEMENTER,
417 ARM_IMPLEMENTER,
418 QUALCOMM_IMPLEMENTER
419 };
420
421
415 // Feature flags bit positions. They are mostly based on the CPUID spec. 422 // Feature flags bit positions. They are mostly based on the CPUID spec.
416 // (We assign CPUID itself to one of the currently reserved bits -- 423 // (We assign CPUID itself to one of the currently reserved bits --
417 // feel free to change this if needed.) 424 // feel free to change this if needed.)
418 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX. 425 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX.
419 enum CpuFeature { SSE4_1 = 32 + 19, // x86 426 enum CpuFeature { SSE4_1 = 32 + 19, // x86
420 SSE3 = 32 + 0, // x86 427 SSE3 = 32 + 0, // x86
421 SSE2 = 26, // x86 428 SSE2 = 26, // x86
422 CMOV = 15, // x86 429 CMOV = 15, // x86
423 RDTSC = 4, // x86 430 RDTSC = 4, // x86
424 CPUID = 10, // x86 431 CPUID = 10, // x86
425 VFP3 = 1, // ARM 432 VFP3 = 1, // ARM
426 ARMv7 = 2, // ARM 433 ARMv7 = 2, // ARM
427 VFP2 = 3, // ARM 434 VFP2 = 3, // ARM
428 SUDIV = 4, // ARM 435 SUDIV = 4, // ARM
429 UNALIGNED_ACCESSES = 5, // ARM 436 UNALIGNED_ACCESSES = 5, // ARM
437 MOVW_MOVT_IMMEDIATE_LOADS = 6, // ARM
430 SAHF = 0, // x86 438 SAHF = 0, // x86
431 FPU = 1}; // MIPS 439 FPU = 1}; // MIPS
432 440
433 441
434 // Used to specify if a macro instruction must perform a smi check on tagged 442 // Used to specify if a macro instruction must perform a smi check on tagged
435 // values. 443 // values.
436 enum SmiCheckType { 444 enum SmiCheckType {
437 DONT_DO_SMI_CHECK, 445 DONT_DO_SMI_CHECK,
438 DO_SMI_CHECK 446 DO_SMI_CHECK
439 }; 447 };
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559 567
560 enum ClearExceptionFlag { 568 enum ClearExceptionFlag {
561 KEEP_EXCEPTION, 569 KEEP_EXCEPTION,
562 CLEAR_EXCEPTION 570 CLEAR_EXCEPTION
563 }; 571 };
564 572
565 573
566 } } // namespace v8::internal 574 } } // namespace v8::internal
567 575
568 #endif // V8_V8GLOBALS_H_ 576 #endif // V8_V8GLOBALS_H_
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