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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1968 *encoding = (hi >> 16) & 0xf; // Low nybble. | 1968 *encoding = (hi >> 16) & 0xf; // Low nybble. |
1969 *encoding |= (hi >> 4) & 0x70000; // Low three bits of the high nybble. | 1969 *encoding |= (hi >> 4) & 0x70000; // Low three bits of the high nybble. |
1970 *encoding |= (hi >> 12) & 0x80000; // Top bit of the high nybble. | 1970 *encoding |= (hi >> 12) & 0x80000; // Top bit of the high nybble. |
1971 | 1971 |
1972 return true; | 1972 return true; |
1973 } | 1973 } |
1974 | 1974 |
1975 | 1975 |
1976 void Assembler::vmov(const DwVfpRegister dst, | 1976 void Assembler::vmov(const DwVfpRegister dst, |
1977 double imm, | 1977 double imm, |
1978 const Register scratch, | |
1979 const Condition cond) { | 1978 const Condition cond) { |
1980 // Dd = immediate | 1979 // Dd = immediate |
1981 // Instruction details available in ARM DDI 0406B, A8-640. | 1980 // Instruction details available in ARM DDI 0406B, A8-640. |
1982 ASSERT(CpuFeatures::IsEnabled(VFP2)); | 1981 ASSERT(CpuFeatures::IsEnabled(VFP2)); |
1983 | 1982 |
1984 uint32_t enc; | 1983 uint32_t enc; |
1985 if (CpuFeatures::IsSupported(VFP3) && FitsVMOVDoubleImmediate(imm, &enc)) { | 1984 if (CpuFeatures::IsSupported(VFP3) && FitsVMOVDoubleImmediate(imm, &enc)) { |
1986 // The double can be encoded in the instruction. | 1985 // The double can be encoded in the instruction. |
1987 emit(cond | 0xE*B24 | 0xB*B20 | dst.code()*B12 | 0xB*B8 | enc); | 1986 emit(cond | 0xE*B24 | 0xB*B20 | dst.code()*B12 | 0xB*B8 | enc); |
1988 } else { | 1987 } else { |
1989 // Synthesise the double from ARM immediates. This could be implemented | 1988 // Synthesise the double from ARM immediates. This could be implemented |
1990 // using vldr from a constant pool. | 1989 // using vldr from a constant pool. |
1991 uint32_t lo, hi; | 1990 uint32_t lo, hi; |
1992 DoubleAsTwoUInt32(imm, &lo, &hi); | 1991 DoubleAsTwoUInt32(imm, &lo, &hi); |
1993 mov(ip, Operand(lo)); | |
1994 | 1992 |
1995 if (scratch.is(no_reg)) { | 1993 if (lo == hi) { |
| 1994 // If the lo and hi parts of the double are equal, the literal is easier |
| 1995 // to create. This is the case with 0.0. |
| 1996 mov(ip, Operand(lo)); |
| 1997 vmov(dst, ip, ip); |
| 1998 } else { |
1996 // Move the low part of the double into the lower of the corresponsing S | 1999 // Move the low part of the double into the lower of the corresponsing S |
1997 // registers of D register dst. | 2000 // registers of D register dst. |
| 2001 mov(ip, Operand(lo)); |
1998 vmov(dst.low(), ip, cond); | 2002 vmov(dst.low(), ip, cond); |
1999 | 2003 |
2000 // Move the high part of the double into the higher of the corresponsing S | 2004 // Move the high part of the double into the higher of the corresponsing S |
2001 // registers of D register dst. | 2005 // registers of D register dst. |
2002 mov(ip, Operand(hi)); | 2006 mov(ip, Operand(hi)); |
2003 vmov(dst.high(), ip, cond); | 2007 vmov(dst.high(), ip, cond); |
2004 } else { | |
2005 // Move the low and high parts of the double to a D register in one | |
2006 // instruction. | |
2007 mov(scratch, Operand(hi)); | |
2008 vmov(dst, ip, scratch, cond); | |
2009 } | 2008 } |
2010 } | 2009 } |
2011 } | 2010 } |
2012 | 2011 |
2013 | 2012 |
2014 void Assembler::vmov(const SwVfpRegister dst, | 2013 void Assembler::vmov(const SwVfpRegister dst, |
2015 const SwVfpRegister src, | 2014 const SwVfpRegister src, |
2016 const Condition cond) { | 2015 const Condition cond) { |
2017 // Sd = Sm | 2016 // Sd = Sm |
2018 // Instruction details available in ARM DDI 0406B, A8-642. | 2017 // Instruction details available in ARM DDI 0406B, A8-642. |
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2689 | 2688 |
2690 // Since a constant pool was just emitted, move the check offset forward by | 2689 // Since a constant pool was just emitted, move the check offset forward by |
2691 // the standard interval. | 2690 // the standard interval. |
2692 next_buffer_check_ = pc_offset() + kCheckPoolInterval; | 2691 next_buffer_check_ = pc_offset() + kCheckPoolInterval; |
2693 } | 2692 } |
2694 | 2693 |
2695 | 2694 |
2696 } } // namespace v8::internal | 2695 } } // namespace v8::internal |
2697 | 2696 |
2698 #endif // V8_TARGET_ARCH_ARM | 2697 #endif // V8_TARGET_ARCH_ARM |
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