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Issue 11027060: Faster 64-bit right-shift for the ia32 compiler. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: addressed comments Created 8 years, 2 months ago
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1 // Copyright (c) 2012, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2012, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" 5 #include "vm/globals.h"
6 #if defined(TARGET_ARCH_IA32) 6 #if defined(TARGET_ARCH_IA32)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/heap.h" 9 #include "vm/heap.h"
10 #include "vm/memory_region.h" 10 #include "vm/memory_region.h"
(...skipping 1202 matching lines...) Expand 10 before | Expand all | Expand 10 after
1213 EmitOperand(1, address); 1213 EmitOperand(1, address);
1214 } 1214 }
1215 1215
1216 1216
1217 void Assembler::shll(Register reg, const Immediate& imm) { 1217 void Assembler::shll(Register reg, const Immediate& imm) {
1218 EmitGenericShift(4, reg, imm); 1218 EmitGenericShift(4, reg, imm);
1219 } 1219 }
1220 1220
1221 1221
1222 void Assembler::shll(Register operand, Register shifter) { 1222 void Assembler::shll(Register operand, Register shifter) {
1223 EmitGenericShift(4, operand, shifter); 1223 EmitGenericShift(4, Operand(operand), shifter);
1224 } 1224 }
1225 1225
1226 1226
1227 void Assembler::shrl(Register reg, const Immediate& imm) { 1227 void Assembler::shrl(Register reg, const Immediate& imm) {
1228 EmitGenericShift(5, reg, imm); 1228 EmitGenericShift(5, reg, imm);
1229 } 1229 }
1230 1230
1231 1231
1232 void Assembler::shrl(Register operand, Register shifter) { 1232 void Assembler::shrl(Register operand, Register shifter) {
1233 EmitGenericShift(5, operand, shifter); 1233 EmitGenericShift(5, Operand(operand), shifter);
1234 } 1234 }
1235 1235
1236 1236
1237 void Assembler::sarl(Register reg, const Immediate& imm) { 1237 void Assembler::sarl(Register reg, const Immediate& imm) {
1238 EmitGenericShift(7, reg, imm); 1238 EmitGenericShift(7, reg, imm);
1239 } 1239 }
1240 1240
1241 1241
1242 void Assembler::sarl(Register operand, Register shifter) { 1242 void Assembler::sarl(Register operand, Register shifter) {
1243 EmitGenericShift(7, operand, shifter); 1243 EmitGenericShift(7, Operand(operand), shifter);
1244 }
1245
1246
1247 void Assembler::sarl(const Address& address, Register shifter) {
1248 EmitGenericShift(7, Operand(address), shifter);
1244 } 1249 }
1245 1250
1246 1251
1247 void Assembler::shld(Register dst, Register src) { 1252 void Assembler::shld(Register dst, Register src) {
1248 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1253 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1249 EmitUint8(0x0F); 1254 EmitUint8(0x0F);
1250 EmitUint8(0xA5); 1255 EmitUint8(0xA5);
1251 EmitRegisterOperand(src, dst); 1256 EmitRegisterOperand(src, dst);
1252 } 1257 }
1253 1258
1254 1259
1260 void Assembler::shrd(Register dst, Register src) {
1261 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1262 EmitUint8(0x0F);
1263 EmitUint8(0xAD);
1264 EmitRegisterOperand(src, dst);
1265 }
1266
1267
1268 void Assembler::shrd(const Address& dst, Register src) {
1269 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1270 EmitUint8(0x0F);
1271 EmitUint8(0xAD);
1272 EmitOperand(src, Operand(dst));
1273 }
1274
1275
1255 void Assembler::negl(Register reg) { 1276 void Assembler::negl(Register reg) {
1256 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1277 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1257 EmitUint8(0xF7); 1278 EmitUint8(0xF7);
1258 EmitOperand(3, Operand(reg)); 1279 EmitOperand(3, Operand(reg));
1259 } 1280 }
1260 1281
1261 1282
1262 void Assembler::notl(Register reg) { 1283 void Assembler::notl(Register reg) {
1263 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1284 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1264 EmitUint8(0xF7); 1285 EmitUint8(0xF7);
(...skipping 634 matching lines...) Expand 10 before | Expand all | Expand 10 after
1899 EmitOperand(rm, Operand(reg)); 1920 EmitOperand(rm, Operand(reg));
1900 } else { 1921 } else {
1901 EmitUint8(0xC1); 1922 EmitUint8(0xC1);
1902 EmitOperand(rm, Operand(reg)); 1923 EmitOperand(rm, Operand(reg));
1903 EmitUint8(imm.value() & 0xFF); 1924 EmitUint8(imm.value() & 0xFF);
1904 } 1925 }
1905 } 1926 }
1906 1927
1907 1928
1908 void Assembler::EmitGenericShift(int rm, 1929 void Assembler::EmitGenericShift(int rm,
1909 Register operand, 1930 const Operand& operand,
1910 Register shifter) { 1931 Register shifter) {
1911 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1932 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1912 ASSERT(shifter == ECX); 1933 ASSERT(shifter == ECX);
1913 EmitUint8(0xD3); 1934 EmitUint8(0xD3);
1914 EmitOperand(rm, Operand(operand)); 1935 EmitOperand(rm, Operand(operand));
1915 } 1936 }
1916 1937
1917 1938
1918 void Assembler::LoadClassId(Register result, Register object) { 1939 void Assembler::LoadClassId(Register result, Register object) {
1919 ASSERT(RawObject::kClassIdTagBit == 16); 1940 ASSERT(RawObject::kClassIdTagBit == 16);
(...skipping 81 matching lines...) Expand 10 before | Expand all | Expand 10 after
2001 2022
2002 const char* Assembler::XmmRegisterName(XmmRegister reg) { 2023 const char* Assembler::XmmRegisterName(XmmRegister reg) {
2003 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters)); 2024 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
2004 return xmm_reg_names[reg]; 2025 return xmm_reg_names[reg];
2005 } 2026 }
2006 2027
2007 2028
2008 } // namespace dart 2029 } // namespace dart
2009 2030
2010 #endif // defined TARGET_ARCH_IA32 2031 #endif // defined TARGET_ARCH_IA32
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