Move validator_x86_XX.rl out of unreviewed.

src/trusted/validator_ragel/validator_internal.h

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /*
  * This file contains common parts of x86-32 and x86-64 internals (inline
  * functions and defines).
  */
 
 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_RAGEL_VALIDATOR_INTERNAL_H_
 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_RAGEL_VALIDATOR_INTERNAL_H_
 
 #include "native_client/src/shared/platform/nacl_check.h"
 #include "native_client/src/shared/utils/types.h"
-#include "native_client/src/trusted/validator_ragel/unreviewed/decoding.h"
+#include "native_client/src/trusted/validator_ragel/decoding.h"
 #include "native_client/src/trusted/validator_ragel/validator.h"
 
 /* Maximum set of R-DFA allowable CPUID features.  */
 extern const NaClCPUFeaturesX86 kValidatorCPUIDFeatures;
 
 /* Macroses to suppport CPUID handling.  */

[halyavin, 2013/03/18 11:58:44]

misprint: support.

[khim, 2013/03/19 14:54:46]

Done.

 #define SET_CPU_FEATURE(F) \

[halyavin, 2013/03/18 11:58:44]

Comment what is F and F_Allowed (variable? constant? macro? enum?).

[khim, 2013/03/19 14:54:46]

If it'll be anything but macro then "macroses" in the previous line will be a
lie, isn't it?

[halyavin, 2013/03/19 15:02:30]

No. You can create variables with names F and F_Allowed somewhere later and then
use SET_CPU_FEATURE(F).

[khim, 2013/03/21 14:38:17]

This will be a lie since it'll be macro then, not macroSES.

   if (!(F##_Allowed)) { \
     instruction_info_collected |= UNRECOGNIZED_INSTRUCTION; \
   } \
   if (!(F)) { \
     instruction_info_collected |= CPUID_UNSUPPORTED_INSTRUCTION; \
   }
 #define CPUFeature_3DNOW    cpu_features->data[NaClCPUFeatureX86_3DNOW]
 /*
  * AMD documentation claims it's always available if CPUFeature_LM is present,
  * But Intel documentation does not even mention it!
  * Keep it as 3DNow! instruction.
  */
 #define CPUFeature_3DPRFTCH CPUFeature_3DNOW || CPUFeature_PRE
 #define CPUFeature_AES      cpu_features->data[NaClCPUFeatureX86_AES]
 #define CPUFeature_AESAVX   CPUFeature_AES && CPUFeature_AVX

[Vlad Shcherbina, 2013/03/18 15:15:18]

Currently these 'composite' features only refer to atomic features, but I
suggest putting parenthesis just in case. If for example CPUFeature_AVX were
defined as 'CPUFeature_foo || CPUFeature_bar', this line would be incorrect.

[khim, 2013/03/19 14:54:46]

Done.

 #define CPUFeature_AVX      cpu_features->data[NaClCPUFeatureX86_AVX]
 #define CPUFeature_BMI1     cpu_features->data[NaClCPUFeatureX86_BMI1]
 #define CPUFeature_CLFLUSH  cpu_features->data[NaClCPUFeatureX86_CLFLUSH]
 #define CPUFeature_CLMUL    cpu_features->data[NaClCPUFeatureX86_CLMUL]
 #define CPUFeature_CLMULAVX CPUFeature_CLMUL && CPUFeature_AVX
 #define CPUFeature_CMOV     cpu_features->data[NaClCPUFeatureX86_CMOV]
 #define CPUFeature_CMOVx87  CPUFeature_CMOV && CPUFeature_x87
 #define CPUFeature_CX16     cpu_features->data[NaClCPUFeatureX86_CX16]
 #define CPUFeature_CX8      cpu_features->data[NaClCPUFeatureX86_CX8]
 #define CPUFeature_E3DNOW   cpu_features->data[NaClCPUFeatureX86_E3DNOW]
@@ skipping 27 matching lines @@
 #define CPUFeature_TBM      cpu_features->data[NaClCPUFeatureX86_TBM]
 #define CPUFeature_TSC      cpu_features->data[NaClCPUFeatureX86_TSC]
 /*
  * We allow tzcnt unconditionally
  * See http://code.google.com/p/nativeclient/issues/detail?id=2869
  */
 #define CPUFeature_TZCNT    TRUE
 #define CPUFeature_x87      cpu_features->data[NaClCPUFeatureX86_x87]
 #define CPUFeature_XOP      cpu_features->data[NaClCPUFeatureX86_XOP]
 
 #define CPUFeature_3DNOW_Allowed \

[Vlad Shcherbina, 2013/03/18 15:15:18]

Currently macros CPUFeature_<whatever>_Allowed completely duplicate macros
CPUFeature_<whatever>. It can be avoided if these macros take cpu_features (or
maybe even cpu_features->data as argument).

[khim, 2013/03/19 14:54:46]

Done.

   kValidatorCPUIDFeatures.data[NaClCPUFeatureX86_3DNOW]
 /*
  * AMD documentation claims it's always available if CPUFeature_LM is present,
  * But Intel documentation does not even mention it!
  * Keep it as 3DNow! instruction.
  */
 #define CPUFeature_3DPRFTCH_Allowed \
   CPUFeature_3DNOW_Allowed || CPUFeature_PRE_Allowed
 #define CPUFeature_AES_Allowed \
   kValidatorCPUIDFeatures.data[NaClCPUFeatureX86_AES]
@@ skipping 77 matching lines @@
  * See http://code.google.com/p/nativeclient/issues/detail?id=2869
  */
 #define CPUFeature_TZCNT_Allowed TRUE
 #define CPUFeature_x87_Allowed \
   kValidatorCPUIDFeatures.data[NaClCPUFeatureX86_x87]
 #define CPUFeature_XOP_Allowed \
   kValidatorCPUIDFeatures.data[NaClCPUFeatureX86_XOP]
 
 /* Remember some information about instruction for further processing.  */
 #define GET_REX_PREFIX() rex_prefix
 #define SET_REX_PREFIX(P) rex_prefix = (P)

[halyavin, 2013/03/18 11:58:44]

P->PREFIX

[khim, 2013/03/19 14:54:46]

Long live cryptic error messages!

But as I've said before: I don't care anymore. You ask me to mangle the code - I
do that.

 #define GET_VEX_PREFIX2() vex_prefix2
 #define SET_VEX_PREFIX2(P) vex_prefix2 = (P)
 #define GET_VEX_PREFIX3() vex_prefix3
 #define SET_VEX_PREFIX3(P) vex_prefix3 = (P)
 #define SET_MODRM_BASE(N) base = (N)

[halyavin, 2013/03/18 11:58:44]

N->REG?

[khim, 2013/03/19 14:54:46]

Done.

 #define SET_MODRM_INDEX(N) index = (N)
 
 /* Ignore this information for now.  */
 #define SET_DATA16_PREFIX(S)

[halyavin, 2013/03/18 11:58:44]

What is S and P below?

[khim, 2013/03/19 14:54:46]

Expanded (expect cryptic error messages in the future here as well).

 #define SET_REPZ_PREFIX(S)
 #define SET_REPNZ_PREFIX(S)
 #define SET_MODRM_SCALE(S)
 #define SET_DISP_PTR(P)
 #define SET_IMM_PTR(P)
 #define SET_IMM2_PTR(P)
 
 /*
  * Collect information about anyfields (offsets and immediates).
  * Note: we use += below instead of |=. This means two immediate fields will
  * be treated as one.  It's not important for safety.
  */
 #define SET_DISP_TYPE(T) SET_DISP_TYPE_##T

[halyavin, 2013/03/18 11:58:44]

T->TYPE

[khim, 2013/03/19 14:54:46]

Ditto.

 #define SET_DISP_TYPE_DISPNONE
 #define SET_DISP_TYPE_DISP8 (instruction_info_collected += DISPLACEMENT_8BIT)
 #define SET_DISP_TYPE_DISP32 (instruction_info_collected += DISPLACEMENT_32BIT)
 #define SET_IMM_TYPE(T) SET_IMM_TYPE_##T
 /* imm2 field is a flag, not accumulator, like with other immediates  */

[halyavin, 2013/03/18 11:58:44]

like other immediates

[khim, 2013/03/19 14:54:46]

Done.

 #define SET_IMM_TYPE_IMM2 (instruction_info_collected |= IMMEDIATE_2BIT)
 #define SET_IMM_TYPE_IMM8 (instruction_info_collected += IMMEDIATE_8BIT)
 #define SET_IMM_TYPE_IMM16 (instruction_info_collected += IMMEDIATE_16BIT)
 #define SET_IMM_TYPE_IMM32 (instruction_info_collected += IMMEDIATE_32BIT)
 #define SET_IMM_TYPE_IMM64 (instruction_info_collected += IMMEDIATE_64BIT)
 #define SET_IMM2_TYPE(T) SET_IMM2_TYPE_##T

[halyavin, 2013/03/18 11:58:44]

SET_SECOND_IMM_TYPE, T->TYPE

[khim, 2013/03/19 14:54:46]

Done.

 #define SET_IMM2_TYPE_IMM8 \
     (instruction_info_collected += SECOND_IMMEDIATE_8BIT)
 #define SET_IMM2_TYPE_IMM16 \
     (instruction_info_collected += SECOND_IMMEDIATE_16BIT)
 
 /* Mark the destination of a jump instruction and make an early validity check:
  * to jump outside given code region, the target address must be aligned.

[halyavin, 2013/03/18 11:58:44]

jump target outside of given code region must be aligned.

[khim, 2013/03/19 14:54:46]

Done.

  *
  * Returns TRUE iff the jump passes the early validity check.
  */
 static FORCEINLINE int MarkJumpTarget(size_t jump_dest,
                                       bitmap_word *jump_dests,
                                       size_t size) {
   if ((jump_dest & kBundleMask) == 0) {
     return TRUE;
   }
   if (jump_dest >= size) {
@@ skipping 22 matching lines @@
 /*
  * Mark the given addresses as invalid jump target addresses (that is: unmark
  * them).
  */
 static FORCEINLINE void UnmarkValidJumpTargets(size_t address,
                                                size_t bytes,
                                                bitmap_word *valid_targets) {
   BitmapClearBits(valid_targets, address, bytes);
 }
 
 static INLINE Bool ProcessInvalidJumpTargets(

[halyavin, 2013/03/18 14:23:12]

/* Compare valid_targets and jump_dests and call callback for any address in
jump_dests which is not present in valid_targets. */

[khim, 2013/03/19 14:54:46]

Done.

     const uint8_t *data,

[halyavin, 2013/03/18 14:23:12]

data -> code

[khim, 2013/03/19 14:54:46]

Done.

     size_t size,
     bitmap_word *valid_targets,
     bitmap_word *jump_dests,
     ValidationCallbackFunc user_callback,
     void *callback_data) {
   size_t elements = (size + NACL_HOST_WORDSIZE - 1) / NACL_HOST_WORDSIZE;
   size_t i, j;
   Bool result = TRUE;
 
   for (i = 0; i < elements ; i++) {

[halyavin, 2013/03/18 14:23:12]

extra space

[khim, 2013/03/19 14:54:46]

Done.

     bitmap_word jump_dest_mask = jump_dests[i];
     bitmap_word valid_target_mask = valid_targets[i];
     if ((jump_dest_mask & ~valid_target_mask) != 0) {
       for (j = i * NACL_HOST_WORDSIZE; j < (i + 1) * NACL_HOST_WORDSIZE; j++)
         if (BitmapIsBitSet(jump_dests, j) &&
             !BitmapIsBitSet(valid_targets, j)) {
           result &= user_callback(data + j,
                                   data + j,
                                   BAD_JUMP_TARGET,
                                   callback_data);
         }
     }
   }
 
   return result;
 }
 
 
 /*
  * Process rel8_operand.  Note: rip points to the beginning of the next
  * instruction here and x86 encoding guarantees rel8 field is the last one
  * in a current instruction.
  */
 static FORCEINLINE void Rel8Operand(const uint8_t *rip,
                                     const uint8_t* codeblock_start,
                                     bitmap_word *jump_dests,
                                     size_t jumpdests_size,
                                     uint32_t *instruction_info_collected) {
   int8_t offset = (uint8_t) (rip[-1]);

[halyavin, 2013/03/18 14:23:12]

remove uint8_t

[khim, 2013/03/19 14:54:46]

Done.

   size_t jump_dest = offset + (rip - codeblock_start);
 
   if (MarkJumpTarget(jump_dest, jump_dests, jumpdests_size))
     *instruction_info_collected |= RELATIVE_8BIT;
   else
     *instruction_info_collected |= RELATIVE_8BIT | DIRECT_JUMP_OUT_OF_RANGE;
 }
 
 /*
  * Process rel32_operand.  Note: rip points to the beginning of the next
  * instruction here and x86 encoding guarantees rel32 field is the last one
  * in a current instruction.
  */
 static FORCEINLINE void Rel32Operand(const uint8_t *rip,
                                      const uint8_t* codeblock_start,
                                      bitmap_word *jump_dests,
                                      size_t jumpdests_size,
                                      uint32_t *instruction_info_collected) {
   int32_t offset = (rip[-4] + 256U * (rip[-3] + 256U * (
                                        rip[-2] + 256U * ((uint32_t) rip[-1]))));

[halyavin, 2013/03/18 14:23:12]

remove uint32_t

[khim, 2013/03/19 14:54:46]

Done.

   size_t jump_dest = offset + (rip - codeblock_start);
 
   if (MarkJumpTarget(jump_dest, jump_dests, jumpdests_size))
     *instruction_info_collected |= RELATIVE_32BIT;
   else
     *instruction_info_collected |= RELATIVE_32BIT | DIRECT_JUMP_OUT_OF_RANGE;
 }
 
 #endif  /* NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_RAGEL_VALIDATOR_INTERNAL_H_ */