Change table data_processing_immediate to use the new notation. Also

src/trusted/validator_arm/gen/arm32_decode_named_decoder.h

 /*
  * Copyright 2012 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #ifndef NACL_TRUSTED_BUT_NOT_TCB
 #error This file is not meant for use in the TCB
@@ skipping 30 matching lines @@
   // by the table methods above. This speeds up the code since
   // the class decoders need to only be bulit once (and reused
   // for each call to "decode_named").
   const NamedBinary2RegisterBitRangeMsbGeLsb_Bfi_Rule_18_A1_P48 Binary2RegisterBitRangeMsbGeLsb_Bfi_Rule_18_A1_P48_instance_;
   const NamedBinary2RegisterBitRangeNotRnIsPcBitfieldExtract_Sbfx_Rule_154_A1_P308 Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_Sbfx_Rule_154_A1_P308_instance_;
   const NamedBinary2RegisterBitRangeNotRnIsPcBitfieldExtract_Ubfx_Rule_236_A1_P466 Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_Ubfx_Rule_236_A1_P466_instance_;
   const NamedBinary2RegisterImmedShiftedTest_Cmn_Rule_33_A1_P76 Binary2RegisterImmedShiftedTest_Cmn_Rule_33_A1_P76_instance_;
   const NamedBinary2RegisterImmedShiftedTest_Cmp_Rule_36_A1_P82 Binary2RegisterImmedShiftedTest_Cmp_Rule_36_A1_P82_instance_;
   const NamedBinary2RegisterImmedShiftedTest_Teq_Rule_228_A1_P450 Binary2RegisterImmedShiftedTest_Teq_Rule_228_A1_P450_instance_;
   const NamedBinary2RegisterImmedShiftedTest_Tst_Rule_231_A1_P456 Binary2RegisterImmedShiftedTest_Tst_Rule_231_A1_P456_instance_;
-  const NamedBinary2RegisterImmediateOp_Adc_Rule_6_A1_P14 Binary2RegisterImmediateOp_Adc_Rule_6_A1_P14_instance_;
-  const NamedBinary2RegisterImmediateOp_Add_Rule_5_A1_P22 Binary2RegisterImmediateOp_Add_Rule_5_A1_P22_instance_;
-  const NamedBinary2RegisterImmediateOp_And_Rule_11_A1_P34 Binary2RegisterImmediateOp_And_Rule_11_A1_P34_instance_;
-  const NamedBinary2RegisterImmediateOp_Eor_Rule_44_A1_P94 Binary2RegisterImmediateOp_Eor_Rule_44_A1_P94_instance_;
-  const NamedBinary2RegisterImmediateOp_Orr_Rule_113_A1_P228 Binary2RegisterImmediateOp_Orr_Rule_113_A1_P228_instance_;
-  const NamedBinary2RegisterImmediateOp_Rsb_Rule_142_A1_P284 Binary2RegisterImmediateOp_Rsb_Rule_142_A1_P284_instance_;
-  const NamedBinary2RegisterImmediateOp_Rsc_Rule_145_A1_P290 Binary2RegisterImmediateOp_Rsc_Rule_145_A1_P290_instance_;
-  const NamedBinary2RegisterImmediateOp_Sbc_Rule_151_A1_P302 Binary2RegisterImmediateOp_Sbc_Rule_151_A1_P302_instance_;
-  const NamedBinary2RegisterImmediateOp_Sub_Rule_212_A1_P420 Binary2RegisterImmediateOp_Sub_Rule_212_A1_P420_instance_;
+  const NamedBinary2RegisterImmediateOp_ADC_immediate_A1 Binary2RegisterImmediateOp_ADC_immediate_A1_instance_;
+  const NamedBinary2RegisterImmediateOp_ADD_immediate_A1 Binary2RegisterImmediateOp_ADD_immediate_A1_instance_;
+  const NamedBinary2RegisterImmediateOp_AND_immediate_A1 Binary2RegisterImmediateOp_AND_immediate_A1_instance_;
+  const NamedBinary2RegisterImmediateOp_EOR_immediate_A1 Binary2RegisterImmediateOp_EOR_immediate_A1_instance_;
+  const NamedBinary2RegisterImmediateOp_ORR_immediate_A1 Binary2RegisterImmediateOp_ORR_immediate_A1_instance_;
+  const NamedBinary2RegisterImmediateOp_RSB_immediate_A1 Binary2RegisterImmediateOp_RSB_immediate_A1_instance_;
+  const NamedBinary2RegisterImmediateOp_RSC_immediate_A1 Binary2RegisterImmediateOp_RSC_immediate_A1_instance_;
+  const NamedBinary2RegisterImmediateOp_SBC_immediate_A1 Binary2RegisterImmediateOp_SBC_immediate_A1_instance_;
+  const NamedBinary2RegisterImmediateOp_SUB_immediate_A1 Binary2RegisterImmediateOp_SUB_immediate_A1_instance_;
   const NamedBinary3RegisterImmedShiftedOp_Adc_Rule_2_A1_P16 Binary3RegisterImmedShiftedOp_Adc_Rule_2_A1_P16_instance_;
   const NamedBinary3RegisterImmedShiftedOp_Add_Rule_6_A1_P24 Binary3RegisterImmedShiftedOp_Add_Rule_6_A1_P24_instance_;
   const NamedBinary3RegisterImmedShiftedOp_And_Rule_7_A1_P36 Binary3RegisterImmedShiftedOp_And_Rule_7_A1_P36_instance_;
   const NamedBinary3RegisterImmedShiftedOp_Bic_Rule_20_A1_P52 Binary3RegisterImmedShiftedOp_Bic_Rule_20_A1_P52_instance_;
   const NamedBinary3RegisterImmedShiftedOp_Eor_Rule_45_A1_P96 Binary3RegisterImmedShiftedOp_Eor_Rule_45_A1_P96_instance_;
   const NamedBinary3RegisterImmedShiftedOp_Orr_Rule_114_A1_P230 Binary3RegisterImmedShiftedOp_Orr_Rule_114_A1_P230_instance_;
   const NamedBinary3RegisterImmedShiftedOp_Rsb_Rule_143_P286 Binary3RegisterImmedShiftedOp_Rsb_Rule_143_P286_instance_;
   const NamedBinary3RegisterImmedShiftedOp_Rsc_Rule_146_A1_P292 Binary3RegisterImmedShiftedOp_Rsc_Rule_146_A1_P292_instance_;
   const NamedBinary3RegisterImmedShiftedOp_Sbc_Rule_152_A1_P304 Binary3RegisterImmedShiftedOp_Sbc_Rule_152_A1_P304_instance_;
   const NamedBinary3RegisterImmedShiftedOp_Sub_Rule_213_A1_P422 Binary3RegisterImmedShiftedOp_Sub_Rule_213_A1_P422_instance_;
@@ skipping 82 matching lines @@
   const NamedBinary4RegisterShiftedOp_ADC_register_shifted_register_A1 Binary4RegisterShiftedOp_ADC_register_shifted_register_A1_instance_;
   const NamedBinary4RegisterShiftedOp_ADD_register_shifted_register_A1 Binary4RegisterShiftedOp_ADD_register_shifted_register_A1_instance_;
   const NamedBinary4RegisterShiftedOp_AND_register_shifted_register_A1 Binary4RegisterShiftedOp_AND_register_shifted_register_A1_instance_;
   const NamedBinary4RegisterShiftedOp_BIC_register_shifted_register_A1 Binary4RegisterShiftedOp_BIC_register_shifted_register_A1_instance_;
   const NamedBinary4RegisterShiftedOp_EOR_register_shifted_register_A1 Binary4RegisterShiftedOp_EOR_register_shifted_register_A1_instance_;
   const NamedBinary4RegisterShiftedOp_ORR_register_shifted_register_A1 Binary4RegisterShiftedOp_ORR_register_shifted_register_A1_instance_;
   const NamedBinary4RegisterShiftedOp_RSB_register_shfited_register_A1 Binary4RegisterShiftedOp_RSB_register_shfited_register_A1_instance_;
   const NamedBinary4RegisterShiftedOp_RSC_register_shifted_register_A1 Binary4RegisterShiftedOp_RSC_register_shifted_register_A1_instance_;
   const NamedBinary4RegisterShiftedOp_SBC_register_shifted_register_A1 Binary4RegisterShiftedOp_SBC_register_shifted_register_A1_instance_;
   const NamedBinary4RegisterShiftedOp_SUB_register_shifted_register_A1 Binary4RegisterShiftedOp_SUB_register_shifted_register_A1_instance_;
-  const NamedBinaryRegisterImmediateTest_Cmn_Rule_32_A1_P74 BinaryRegisterImmediateTest_Cmn_Rule_32_A1_P74_instance_;
-  const NamedBinaryRegisterImmediateTest_Cmp_Rule_35_A1_P80 BinaryRegisterImmediateTest_Cmp_Rule_35_A1_P80_instance_;
-  const NamedBinaryRegisterImmediateTest_Teq_Rule_227_A1_P448 BinaryRegisterImmediateTest_Teq_Rule_227_A1_P448_instance_;
+  const NamedBinaryRegisterImmediateTest_CMN_immediate_A1 BinaryRegisterImmediateTest_CMN_immediate_A1_instance_;
+  const NamedBinaryRegisterImmediateTest_CMP_immediate_A1 BinaryRegisterImmediateTest_CMP_immediate_A1_instance_;
+  const NamedBinaryRegisterImmediateTest_TEQ_immediate_A1 BinaryRegisterImmediateTest_TEQ_immediate_A1_instance_;
   const NamedBranchImmediate24_B_Rule_16_A1_P44 BranchImmediate24_B_Rule_16_A1_P44_instance_;
   const NamedBranchImmediate24_Bl_Blx_Rule_23_A1_P58 BranchImmediate24_Bl_Blx_Rule_23_A1_P58_instance_;
   const NamedBranchToRegister_Blx_Rule_24_A1_P60 BranchToRegister_Blx_Rule_24_A1_P60_instance_;
   const NamedBranchToRegister_Bx_Rule_25_A1_P62 BranchToRegister_Bx_Rule_25_A1_P62_instance_;
   const NamedBreakPointAndConstantPoolHead_Bkpt_Rule_22_A1_P56 BreakPointAndConstantPoolHead_Bkpt_Rule_22_A1_P56_instance_;
   const NamedCondDecoder_Nop_Rule_110_A1_P222 CondDecoder_Nop_Rule_110_A1_P222_instance_;
   const NamedCondDecoder_Yield_Rule_413_A1_P812 CondDecoder_Yield_Rule_413_A1_P812_instance_;
   const NamedCondVfpOp_Vabs_Rule_269_A2_P532 CondVfpOp_Vabs_Rule_269_A2_P532_instance_;
   const NamedCondVfpOp_Vadd_Rule_271_A2_P536 CondVfpOp_Vadd_Rule_271_A2_P536_instance_;
   const NamedCondVfpOp_Vcmp_Vcmpe_Rule_A1 CondVfpOp_Vcmp_Vcmpe_Rule_A1_instance_;
@@ skipping 41 matching lines @@
   const NamedForbiddenCondDecoder_Msr_Rule_Banked_register_A1_B9_1990 ForbiddenCondDecoder_Msr_Rule_Banked_register_A1_B9_1990_instance_;
   const NamedForbiddenCondDecoder_Msr_Rule_Banked_register_A1_B9_1992 ForbiddenCondDecoder_Msr_Rule_Banked_register_A1_B9_1992_instance_;
   const NamedForbiddenCondDecoder_Sev_Rule_158_A1_P316 ForbiddenCondDecoder_Sev_Rule_158_A1_P316_instance_;
   const NamedForbiddenCondDecoder_Smc_Rule_B6_1_9_P18 ForbiddenCondDecoder_Smc_Rule_B6_1_9_P18_instance_;
   const NamedForbiddenCondDecoder_Stc_Rule_A2 ForbiddenCondDecoder_Stc_Rule_A2_instance_;
   const NamedForbiddenCondDecoder_Stm_Rule_11_B6_A1_P22 ForbiddenCondDecoder_Stm_Rule_11_B6_A1_P22_instance_;
   const NamedForbiddenCondDecoder_Strt_Rule_A1 ForbiddenCondDecoder_Strt_Rule_A1_instance_;
   const NamedForbiddenCondDecoder_Strt_Rule_A2 ForbiddenCondDecoder_Strt_Rule_A2_instance_;
   const NamedForbiddenCondDecoder_Strtb_Rule_A1 ForbiddenCondDecoder_Strtb_Rule_A1_instance_;
   const NamedForbiddenCondDecoder_Strtb_Rule_A2 ForbiddenCondDecoder_Strtb_Rule_A2_instance_;
-  const NamedForbiddenCondDecoder_Subs_Pc_Lr_and_related_instructions_Rule_A1a ForbiddenCondDecoder_Subs_Pc_Lr_and_related_instructions_Rule_A1a_instance_;
-  const NamedForbiddenCondDecoder_Subs_Pc_Lr_and_related_instructions_Rule_A1b ForbiddenCondDecoder_Subs_Pc_Lr_and_related_instructions_Rule_A1b_instance_;
   const NamedForbiddenCondDecoder_Svc_Rule_A1 ForbiddenCondDecoder_Svc_Rule_A1_instance_;
   const NamedForbiddenCondDecoder_Wfe_Rule_411_A1_P808 ForbiddenCondDecoder_Wfe_Rule_411_A1_P808_instance_;
   const NamedForbiddenCondDecoder_Wfi_Rule_412_A1_P810 ForbiddenCondDecoder_Wfi_Rule_412_A1_P810_instance_;
   const NamedForbiddenCondDecoder_extra_load_store_instructions_unpriviledged ForbiddenCondDecoder_extra_load_store_instructions_unpriviledged_instance_;
   const NamedForbiddenUncondDecoder_Blx_Rule_23_A2_P58 ForbiddenUncondDecoder_Blx_Rule_23_A2_P58_instance_;
   const NamedForbiddenUncondDecoder_Cdp2_Rule_28_A2_P68 ForbiddenUncondDecoder_Cdp2_Rule_28_A2_P68_instance_;
   const NamedForbiddenUncondDecoder_Clrex_Rule_30_A1_P70 ForbiddenUncondDecoder_Clrex_Rule_30_A1_P70_instance_;
   const NamedForbiddenUncondDecoder_Cps_Rule_b6_1_1_A1_B6_3 ForbiddenUncondDecoder_Cps_Rule_b6_1_1_A1_B6_3_instance_;
   const NamedForbiddenUncondDecoder_Ldc2_Rule_51_A2_P106 ForbiddenUncondDecoder_Ldc2_Rule_51_A2_P106_instance_;
   const NamedForbiddenUncondDecoder_Ldc2_Rule_52_A2_P108 ForbiddenUncondDecoder_Ldc2_Rule_52_A2_P108_instance_;
@@ skipping 31 matching lines @@
   const NamedLoadExclusive2RegisterOp_Ldrexh_Rule_72_A1_P148 LoadExclusive2RegisterOp_Ldrexh_Rule_72_A1_P148_instance_;
   const NamedLoadRegisterList_Ldm_Ldmia_Ldmfd_Rule_53_A1_P110 LoadRegisterList_Ldm_Ldmia_Ldmfd_Rule_53_A1_P110_instance_;
   const NamedLoadRegisterList_Ldmda_Ldmfa_Rule_54_A1_P112 LoadRegisterList_Ldmda_Ldmfa_Rule_54_A1_P112_instance_;
   const NamedLoadRegisterList_Ldmdb_Ldmea_Rule_55_A1_P114 LoadRegisterList_Ldmdb_Ldmea_Rule_55_A1_P114_instance_;
   const NamedLoadRegisterList_Ldmib_Ldmed_Rule_56_A1_P116 LoadRegisterList_Ldmib_Ldmed_Rule_56_A1_P116_instance_;
   const NamedLoadRegisterList_Pop_Rule_A1 LoadRegisterList_Pop_Rule_A1_instance_;
   const NamedLoadVectorRegister_Vldr_Rule_320_A1_A2_P628 LoadVectorRegister_Vldr_Rule_320_A1_A2_P628_instance_;
   const NamedLoadVectorRegisterList_Vldm_Rule_318_A1_A2_P626 LoadVectorRegisterList_Vldm_Rule_318_A1_A2_P626_instance_;
   const NamedLoadVectorRegisterList_Vldm_Rule_319_A1_A2_P626 LoadVectorRegisterList_Vldm_Rule_319_A1_A2_P626_instance_;
   const NamedLoadVectorRegisterList_Vpop_Rule_354_A1_A2_P694 LoadVectorRegisterList_Vpop_Rule_354_A1_A2_P694_instance_;
-  const NamedMaskedBinary2RegisterImmediateOp_Bic_Rule_19_A1_P50 MaskedBinary2RegisterImmediateOp_Bic_Rule_19_A1_P50_instance_;
-  const NamedMaskedBinaryRegisterImmediateTest_Tst_Rule_230_A1_P454 MaskedBinaryRegisterImmediateTest_Tst_Rule_230_A1_P454_instance_;
+  const NamedMaskedBinary2RegisterImmediateOp_BIC_immediate_A1 MaskedBinary2RegisterImmediateOp_BIC_immediate_A1_instance_;
+  const NamedMaskedBinaryRegisterImmediateTest_TST_immediate_A1 MaskedBinaryRegisterImmediateTest_TST_immediate_A1_instance_;
   const NamedMoveDoubleVfpRegisterOp_Vmov_one_D_Rule_A1 MoveDoubleVfpRegisterOp_Vmov_one_D_Rule_A1_instance_;
   const NamedMoveDoubleVfpRegisterOp_Vmov_two_S_Rule_A1 MoveDoubleVfpRegisterOp_Vmov_two_S_Rule_A1_instance_;
   const NamedMoveImmediate12ToApsr_Msr_Rule_103_A1_P208 MoveImmediate12ToApsr_Msr_Rule_103_A1_P208_instance_;
   const NamedMoveVfpRegisterOp_Vmov_Rule_330_A1_P648 MoveVfpRegisterOp_Vmov_Rule_330_A1_P648_instance_;
   const NamedMoveVfpRegisterOpWithTypeSel_Vmov_Rule_328_A1_P644 MoveVfpRegisterOpWithTypeSel_Vmov_Rule_328_A1_P644_instance_;
   const NamedMoveVfpRegisterOpWithTypeSel_Vmov_Rule_329_A1_P646 MoveVfpRegisterOpWithTypeSel_Vmov_Rule_329_A1_P646_instance_;
   const NamedNotImplemented_None NotImplemented_None_instance_;
   const NamedPreloadRegisterImm12Op_Pld_Rule_117_A1_P236 PreloadRegisterImm12Op_Pld_Rule_117_A1_P236_instance_;
   const NamedPreloadRegisterImm12Op_Pld_Rule_118_A1_P238 PreloadRegisterImm12Op_Pld_Rule_118_A1_P238_instance_;
   const NamedPreloadRegisterImm12Op_Pldw_Rule_117_A1_P236 PreloadRegisterImm12Op_Pldw_Rule_117_A1_P236_instance_;
@@ skipping 17 matching lines @@
   const NamedStoreExclusive3RegisterOp_Strexh_Rule_205_A1_P406 StoreExclusive3RegisterOp_Strexh_Rule_205_A1_P406_instance_;
   const NamedStoreRegisterList_Push_Rule_A1 StoreRegisterList_Push_Rule_A1_instance_;
   const NamedStoreRegisterList_Stm_Stmia_Stmea_Rule_189_A1_P374 StoreRegisterList_Stm_Stmia_Stmea_Rule_189_A1_P374_instance_;
   const NamedStoreRegisterList_Stmda_Stmed_Rule_190_A1_P376 StoreRegisterList_Stmda_Stmed_Rule_190_A1_P376_instance_;
   const NamedStoreRegisterList_Stmdb_Stmfd_Rule_191_A1_P378 StoreRegisterList_Stmdb_Stmfd_Rule_191_A1_P378_instance_;
   const NamedStoreRegisterList_Stmib_Stmfa_Rule_192_A1_P380 StoreRegisterList_Stmib_Stmfa_Rule_192_A1_P380_instance_;
   const NamedStoreVectorRegister_Vstr_Rule_400_A1_A2_P786 StoreVectorRegister_Vstr_Rule_400_A1_A2_P786_instance_;
   const NamedStoreVectorRegisterList_Vpush_355_A1_A2_P696 StoreVectorRegisterList_Vpush_355_A1_A2_P696_instance_;
   const NamedStoreVectorRegisterList_Vstm_Rule_399_A1_A2_P784 StoreVectorRegisterList_Vstm_Rule_399_A1_A2_P784_instance_;
   const NamedUnary1RegisterBitRangeMsbGeLsb_Bfc_17_A1_P46 Unary1RegisterBitRangeMsbGeLsb_Bfc_17_A1_P46_instance_;
-  const NamedUnary1RegisterImmediateOp_Adr_Rule_10_A1_P32 Unary1RegisterImmediateOp_Adr_Rule_10_A1_P32_instance_;
-  const NamedUnary1RegisterImmediateOp_Adr_Rule_10_A2_P32 Unary1RegisterImmediateOp_Adr_Rule_10_A2_P32_instance_;
-  const NamedUnary1RegisterImmediateOp_Mov_Rule_96_A1_P194 Unary1RegisterImmediateOp_Mov_Rule_96_A1_P194_instance_;
+  const NamedUnary1RegisterImmediateOp_ADR_A1 Unary1RegisterImmediateOp_ADR_A1_instance_;
+  const NamedUnary1RegisterImmediateOp_ADR_A2 Unary1RegisterImmediateOp_ADR_A2_instance_;
+  const NamedUnary1RegisterImmediateOp_MOV_immediate_A1 Unary1RegisterImmediateOp_MOV_immediate_A1_instance_;
+  const NamedUnary1RegisterImmediateOp_MVN_immediate_A1 Unary1RegisterImmediateOp_MVN_immediate_A1_instance_;
   const NamedUnary1RegisterImmediateOp_Mov_Rule_96_A2_P194 Unary1RegisterImmediateOp_Mov_Rule_96_A2_P194_instance_;
   const NamedUnary1RegisterImmediateOp_Mov_Rule_99_A1_P200 Unary1RegisterImmediateOp_Mov_Rule_99_A1_P200_instance_;
-  const NamedUnary1RegisterImmediateOp_Mvn_Rule_106_A1_P214 Unary1RegisterImmediateOp_Mvn_Rule_106_A1_P214_instance_;
   const NamedUnary1RegisterSet_Mrs_Rule_102_A1_P206_Or_B6_10 Unary1RegisterSet_Mrs_Rule_102_A1_P206_Or_B6_10_instance_;
   const NamedUnary1RegisterUse_Msr_Rule_104_A1_P210 Unary1RegisterUse_Msr_Rule_104_A1_P210_instance_;
   const NamedUnary2RegisterImmedShiftedOp_Asr_Rule_14_A1_P40 Unary2RegisterImmedShiftedOp_Asr_Rule_14_A1_P40_instance_;
   const NamedUnary2RegisterImmedShiftedOp_Lsl_Rule_88_A1_P178 Unary2RegisterImmedShiftedOp_Lsl_Rule_88_A1_P178_instance_;
   const NamedUnary2RegisterImmedShiftedOp_Lsr_Rule_90_A1_P182 Unary2RegisterImmedShiftedOp_Lsr_Rule_90_A1_P182_instance_;
   const NamedUnary2RegisterImmedShiftedOp_Mvn_Rule_107_A1_P216 Unary2RegisterImmedShiftedOp_Mvn_Rule_107_A1_P216_instance_;
   const NamedUnary2RegisterImmedShiftedOp_Ror_Rule_139_A1_P278 Unary2RegisterImmedShiftedOp_Ror_Rule_139_A1_P278_instance_;
   const NamedUnary2RegisterImmedShiftedOpRegsNotPc_Sxtb16_Rule_224_A1_P442 Unary2RegisterImmedShiftedOpRegsNotPc_Sxtb16_Rule_224_A1_P442_instance_;
   const NamedUnary2RegisterImmedShiftedOpRegsNotPc_Sxtb_Rule_223_A1_P440 Unary2RegisterImmedShiftedOpRegsNotPc_Sxtb_Rule_223_A1_P440_instance_;
   const NamedUnary2RegisterOp_Mov_Rule_97_A1_P196 Unary2RegisterOp_Mov_Rule_97_A1_P196_instance_;
@@ skipping 17 matching lines @@
   const NamedUndefinedCondDecoder_Undefined_A5_2_5_0111 UndefinedCondDecoder_Undefined_A5_2_5_0111_instance_;
   const NamedUndefinedCondDecoder_Undefined_A5_6 UndefinedCondDecoder_Undefined_A5_6_instance_;
   const NamedUnpredictableUncondDecoder_Unpredictable UnpredictableUncondDecoder_Unpredictable_instance_;
   const NamedVfpMrsOp_Vmrs_Rule_335_A1_P658 VfpMrsOp_Vmrs_Rule_335_A1_P658_instance_;
   const NamedVfpUsesRegOp_Vmsr_Rule_336_A1_P660 VfpUsesRegOp_Vmsr_Rule_336_A1_P660_instance_;
   const NamedBranch_B_Rule_16_A1_P44 Branch_B_Rule_16_A1_P44_instance_;
   const NamedBranch_Bl_Blx_Rule_23_A1_P58 Branch_Bl_Blx_Rule_23_A1_P58_instance_;
   const NamedBreakpoint_Bkpt_Rule_22_A1_P56 Breakpoint_Bkpt_Rule_22_A1_P56_instance_;
   const NamedBxBlx_Blx_Rule_24_A1_P60 BxBlx_Blx_Rule_24_A1_P60_instance_;
   const NamedBxBlx_Bx_Rule_25_A1_P62 BxBlx_Bx_Rule_25_A1_P62_instance_;
+  const NamedDefs12To15_ADC_immediate_A1 Defs12To15_ADC_immediate_A1_instance_;
+  const NamedDefs12To15_ADD_immediate_A1 Defs12To15_ADD_immediate_A1_instance_;
+  const NamedDefs12To15_ADR_A1 Defs12To15_ADR_A1_instance_;
+  const NamedDefs12To15_ADR_A2 Defs12To15_ADR_A2_instance_;
+  const NamedDefs12To15_AND_immediate_A1 Defs12To15_AND_immediate_A1_instance_;
   const NamedDefs12To15_Adc_Rule_2_A1_P16 Defs12To15_Adc_Rule_2_A1_P16_instance_;
-  const NamedDefs12To15_Adc_Rule_6_A1_P14 Defs12To15_Adc_Rule_6_A1_P14_instance_;
-  const NamedDefs12To15_Add_Rule_5_A1_P22 Defs12To15_Add_Rule_5_A1_P22_instance_;
   const NamedDefs12To15_Add_Rule_6_A1_P24 Defs12To15_Add_Rule_6_A1_P24_instance_;
-  const NamedDefs12To15_Adr_Rule_10_A1_P32 Defs12To15_Adr_Rule_10_A1_P32_instance_;
-  const NamedDefs12To15_Adr_Rule_10_A2_P32 Defs12To15_Adr_Rule_10_A2_P32_instance_;
-  const NamedDefs12To15_And_Rule_11_A1_P34 Defs12To15_And_Rule_11_A1_P34_instance_;
   const NamedDefs12To15_And_Rule_7_A1_P36 Defs12To15_And_Rule_7_A1_P36_instance_;
   const NamedDefs12To15_Asr_Rule_14_A1_P40 Defs12To15_Asr_Rule_14_A1_P40_instance_;
   const NamedDefs12To15_Bic_Rule_20_A1_P52 Defs12To15_Bic_Rule_20_A1_P52_instance_;
-  const NamedDefs12To15_Eor_Rule_44_A1_P94 Defs12To15_Eor_Rule_44_A1_P94_instance_;
+  const NamedDefs12To15_EOR_immediate_A1 Defs12To15_EOR_immediate_A1_instance_;
   const NamedDefs12To15_Eor_Rule_45_A1_P96 Defs12To15_Eor_Rule_45_A1_P96_instance_;
   const NamedDefs12To15_Lsl_Rule_88_A1_P178 Defs12To15_Lsl_Rule_88_A1_P178_instance_;
   const NamedDefs12To15_Lsr_Rule_90_A1_P182 Defs12To15_Lsr_Rule_90_A1_P182_instance_;
-  const NamedDefs12To15_Mov_Rule_96_A1_P194 Defs12To15_Mov_Rule_96_A1_P194_instance_;
+  const NamedDefs12To15_MOV_immediate_A1 Defs12To15_MOV_immediate_A1_instance_;
+  const NamedDefs12To15_MVN_immediate_A1 Defs12To15_MVN_immediate_A1_instance_;
   const NamedDefs12To15_Mov_Rule_96_A2_P194 Defs12To15_Mov_Rule_96_A2_P194_instance_;
   const NamedDefs12To15_Mov_Rule_97_A1_P196 Defs12To15_Mov_Rule_97_A1_P196_instance_;
   const NamedDefs12To15_Mov_Rule_99_A1_P200 Defs12To15_Mov_Rule_99_A1_P200_instance_;
-  const NamedDefs12To15_Mvn_Rule_106_A1_P214 Defs12To15_Mvn_Rule_106_A1_P214_instance_;
   const NamedDefs12To15_Mvn_Rule_107_A1_P216 Defs12To15_Mvn_Rule_107_A1_P216_instance_;
-  const NamedDefs12To15_Orr_Rule_113_A1_P228 Defs12To15_Orr_Rule_113_A1_P228_instance_;
+  const NamedDefs12To15_ORR_immediate_A1 Defs12To15_ORR_immediate_A1_instance_;
   const NamedDefs12To15_Orr_Rule_114_A1_P230 Defs12To15_Orr_Rule_114_A1_P230_instance_;
+  const NamedDefs12To15_RSB_immediate_A1 Defs12To15_RSB_immediate_A1_instance_;
+  const NamedDefs12To15_RSC_immediate_A1 Defs12To15_RSC_immediate_A1_instance_;
   const NamedDefs12To15_Ror_Rule_139_A1_P278 Defs12To15_Ror_Rule_139_A1_P278_instance_;
   const NamedDefs12To15_Rrx_Rule_141_A1_P282 Defs12To15_Rrx_Rule_141_A1_P282_instance_;
-  const NamedDefs12To15_Rsb_Rule_142_A1_P284 Defs12To15_Rsb_Rule_142_A1_P284_instance_;
   const NamedDefs12To15_Rsb_Rule_143_P286 Defs12To15_Rsb_Rule_143_P286_instance_;
-  const NamedDefs12To15_Rsc_Rule_145_A1_P290 Defs12To15_Rsc_Rule_145_A1_P290_instance_;
   const NamedDefs12To15_Rsc_Rule_146_A1_P292 Defs12To15_Rsc_Rule_146_A1_P292_instance_;
-  const NamedDefs12To15_Sbc_Rule_151_A1_P302 Defs12To15_Sbc_Rule_151_A1_P302_instance_;
+  const NamedDefs12To15_SBC_immediate_A1 Defs12To15_SBC_immediate_A1_instance_;
+  const NamedDefs12To15_SUB_immediate_A1 Defs12To15_SUB_immediate_A1_instance_;
   const NamedDefs12To15_Sbc_Rule_152_A1_P304 Defs12To15_Sbc_Rule_152_A1_P304_instance_;
-  const NamedDefs12To15_Sub_Rule_212_A1_P420 Defs12To15_Sub_Rule_212_A1_P420_instance_;
   const NamedDefs12To15_Sub_Rule_213_A1_P422 Defs12To15_Sub_Rule_213_A1_P422_instance_;
   const NamedDefs12To15CondsDontCareMsbGeLsb_Bfi_Rule_18_A1_P48 Defs12To15CondsDontCareMsbGeLsb_Bfi_Rule_18_A1_P48_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Rbit_Rule_134_A1_P270 Defs12To15CondsDontCareRdRnNotPc_Rbit_Rule_134_A1_P270_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Rev16_Rule_136_A1_P274 Defs12To15CondsDontCareRdRnNotPc_Rev16_Rule_136_A1_P274_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Rev_Rule_135_A1_P272 Defs12To15CondsDontCareRdRnNotPc_Rev_Rule_135_A1_P272_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Revsh_Rule_137_A1_P276 Defs12To15CondsDontCareRdRnNotPc_Revsh_Rule_137_A1_P276_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Ssat16_Rule_184_A1_P364 Defs12To15CondsDontCareRdRnNotPc_Ssat16_Rule_184_A1_P364_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Ssat_Rule_183_A1_P362 Defs12To15CondsDontCareRdRnNotPc_Ssat_Rule_183_A1_P362_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Sxtb16_Rule_224_A1_P442 Defs12To15CondsDontCareRdRnNotPc_Sxtb16_Rule_224_A1_P442_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Sxtb_Rule_223_A1_P440 Defs12To15CondsDontCareRdRnNotPc_Sxtb_Rule_223_A1_P440_instance_;
@@ skipping 88 matching lines @@
   const NamedDefs16To19CondsDontCareRdRaRmRnNotPc_Usada8_Rule_254_A1_P502 Defs16To19CondsDontCareRdRaRmRnNotPc_Usada8_Rule_254_A1_P502_instance_;
   const NamedDefs16To19CondsDontCareRdRmRnNotPc_Mul_Rule_105_A1_P212 Defs16To19CondsDontCareRdRmRnNotPc_Mul_Rule_105_A1_P212_instance_;
   const NamedDefs16To19CondsDontCareRdRmRnNotPc_Sdiv_Rule_A1 Defs16To19CondsDontCareRdRmRnNotPc_Sdiv_Rule_A1_instance_;
   const NamedDefs16To19CondsDontCareRdRmRnNotPc_Smmul_Rule_176_P350 Defs16To19CondsDontCareRdRmRnNotPc_Smmul_Rule_176_P350_instance_;
   const NamedDefs16To19CondsDontCareRdRmRnNotPc_Smuad_Rule_177_P352 Defs16To19CondsDontCareRdRmRnNotPc_Smuad_Rule_177_P352_instance_;
   const NamedDefs16To19CondsDontCareRdRmRnNotPc_Smulwx_Rule_180_A1_P358 Defs16To19CondsDontCareRdRmRnNotPc_Smulwx_Rule_180_A1_P358_instance_;
   const NamedDefs16To19CondsDontCareRdRmRnNotPc_Smulxx_Rule_178_P354 Defs16To19CondsDontCareRdRmRnNotPc_Smulxx_Rule_178_P354_instance_;
   const NamedDefs16To19CondsDontCareRdRmRnNotPc_Smusd_Rule_181_P360 Defs16To19CondsDontCareRdRmRnNotPc_Smusd_Rule_181_P360_instance_;
   const NamedDefs16To19CondsDontCareRdRmRnNotPc_Udiv_Rule_A1 Defs16To19CondsDontCareRdRmRnNotPc_Udiv_Rule_A1_instance_;
   const NamedDefs16To19CondsDontCareRdRmRnNotPc_Usad8_Rule_253_A1_P500 Defs16To19CondsDontCareRdRmRnNotPc_Usad8_Rule_253_A1_P500_instance_;
-  const NamedDontCareInst_Cmn_Rule_32_A1_P74 DontCareInst_Cmn_Rule_32_A1_P74_instance_;
+  const NamedDontCareInst_CMN_immediate_A1 DontCareInst_CMN_immediate_A1_instance_;
+  const NamedDontCareInst_CMP_immediate_A1 DontCareInst_CMP_immediate_A1_instance_;
   const NamedDontCareInst_Cmn_Rule_33_A1_P76 DontCareInst_Cmn_Rule_33_A1_P76_instance_;
-  const NamedDontCareInst_Cmp_Rule_35_A1_P80 DontCareInst_Cmp_Rule_35_A1_P80_instance_;
   const NamedDontCareInst_Cmp_Rule_36_A1_P82 DontCareInst_Cmp_Rule_36_A1_P82_instance_;
   const NamedDontCareInst_Msr_Rule_103_A1_P208 DontCareInst_Msr_Rule_103_A1_P208_instance_;
   const NamedDontCareInst_Nop_Rule_110_A1_P222 DontCareInst_Nop_Rule_110_A1_P222_instance_;
   const NamedDontCareInst_Pld_Rule_117_A1_P236 DontCareInst_Pld_Rule_117_A1_P236_instance_;
   const NamedDontCareInst_Pld_Rule_118_A1_P238 DontCareInst_Pld_Rule_118_A1_P238_instance_;
   const NamedDontCareInst_Pldw_Rule_117_A1_P236 DontCareInst_Pldw_Rule_117_A1_P236_instance_;
   const NamedDontCareInst_Pli_Rule_120_A1_P242 DontCareInst_Pli_Rule_120_A1_P242_instance_;
-  const NamedDontCareInst_Teq_Rule_227_A1_P448 DontCareInst_Teq_Rule_227_A1_P448_instance_;
+  const NamedDontCareInst_TEQ_immediate_A1 DontCareInst_TEQ_immediate_A1_instance_;
   const NamedDontCareInst_Teq_Rule_228_A1_P450 DontCareInst_Teq_Rule_228_A1_P450_instance_;
   const NamedDontCareInst_Tst_Rule_231_A1_P456 DontCareInst_Tst_Rule_231_A1_P456_instance_;
   const NamedDontCareInst_Yield_Rule_413_A1_P812 DontCareInst_Yield_Rule_413_A1_P812_instance_;
   const NamedDontCareInstRdNotPc_Vmsr_Rule_336_A1_P660 DontCareInstRdNotPc_Vmsr_Rule_336_A1_P660_instance_;
   const NamedDontCareInstRnRsRmNotPc_CMN_register_shifted_register_A1 DontCareInstRnRsRmNotPc_CMN_register_shifted_register_A1_instance_;
   const NamedDontCareInstRnRsRmNotPc_CMP_register_shifted_register_A1 DontCareInstRnRsRmNotPc_CMP_register_shifted_register_A1_instance_;
   const NamedDontCareInstRnRsRmNotPc_TEQ_register_shifted_register_A1 DontCareInstRnRsRmNotPc_TEQ_register_shifted_register_A1_instance_;
   const NamedDontCareInstRnRsRmNotPc_TST_register_shifted_register_A1 DontCareInstRnRsRmNotPc_TST_register_shifted_register_A1_instance_;
   const NamedForbidden_Blx_Rule_23_A2_P58 Forbidden_Blx_Rule_23_A2_P58_instance_;
   const NamedForbidden_Bxj_Rule_26_A1_P64 Forbidden_Bxj_Rule_26_A1_P64_instance_;
@@ skipping 31 matching lines @@
   const NamedForbidden_Sev_Rule_158_A1_P316 Forbidden_Sev_Rule_158_A1_P316_instance_;
   const NamedForbidden_Smc_Rule_B6_1_9_P18 Forbidden_Smc_Rule_B6_1_9_P18_instance_;
   const NamedForbidden_Srs_Rule_B6_1_10_A1_B6_20 Forbidden_Srs_Rule_B6_1_10_A1_B6_20_instance_;
   const NamedForbidden_Stc2_Rule_188_A2_P372 Forbidden_Stc2_Rule_188_A2_P372_instance_;
   const NamedForbidden_Stc_Rule_A2 Forbidden_Stc_Rule_A2_instance_;
   const NamedForbidden_Stm_Rule_11_B6_A1_P22 Forbidden_Stm_Rule_11_B6_A1_P22_instance_;
   const NamedForbidden_Strt_Rule_A1 Forbidden_Strt_Rule_A1_instance_;
   const NamedForbidden_Strt_Rule_A2 Forbidden_Strt_Rule_A2_instance_;
   const NamedForbidden_Strtb_Rule_A1 Forbidden_Strtb_Rule_A1_instance_;
   const NamedForbidden_Strtb_Rule_A2 Forbidden_Strtb_Rule_A2_instance_;
-  const NamedForbidden_Subs_Pc_Lr_and_related_instructions_Rule_A1a Forbidden_Subs_Pc_Lr_and_related_instructions_Rule_A1a_instance_;
-  const NamedForbidden_Subs_Pc_Lr_and_related_instructions_Rule_A1b Forbidden_Subs_Pc_Lr_and_related_instructions_Rule_A1b_instance_;
   const NamedForbidden_Svc_Rule_A1 Forbidden_Svc_Rule_A1_instance_;
   const NamedForbidden_Unallocated_hints Forbidden_Unallocated_hints_instance_;
   const NamedForbidden_Wfe_Rule_411_A1_P808 Forbidden_Wfe_Rule_411_A1_P808_instance_;
   const NamedForbidden_Wfi_Rule_412_A1_P810 Forbidden_Wfi_Rule_412_A1_P810_instance_;
   const NamedForbidden_extra_load_store_instructions_unpriviledged Forbidden_extra_load_store_instructions_unpriviledged_instance_;
   const NamedLoadBasedImmedMemory_Ldr_Rule_58_A1_P120 LoadBasedImmedMemory_Ldr_Rule_58_A1_P120_instance_;
   const NamedLoadBasedImmedMemory_Ldr_Rule_59_A1_P122 LoadBasedImmedMemory_Ldr_Rule_59_A1_P122_instance_;
   const NamedLoadBasedImmedMemory_Ldrb_Rule_62_A1_P128 LoadBasedImmedMemory_Ldrb_Rule_62_A1_P128_instance_;
   const NamedLoadBasedImmedMemory_Ldrb_Rule_63_A1_P130 LoadBasedImmedMemory_Ldrb_Rule_63_A1_P130_instance_;
   const NamedLoadBasedImmedMemory_Ldrh_Rule_74_A1_P152 LoadBasedImmedMemory_Ldrh_Rule_74_A1_P152_instance_;
@@ skipping 12 matching lines @@
   const NamedLoadBasedOffsetMemory_Ldrb_Rule_64_A1_P132 LoadBasedOffsetMemory_Ldrb_Rule_64_A1_P132_instance_;
   const NamedLoadBasedOffsetMemory_Ldrh_Rule_76_A1_P156 LoadBasedOffsetMemory_Ldrh_Rule_76_A1_P156_instance_;
   const NamedLoadBasedOffsetMemory_Ldrsb_Rule_80_A1_P164 LoadBasedOffsetMemory_Ldrsb_Rule_80_A1_P164_instance_;
   const NamedLoadBasedOffsetMemory_Ldrsh_Rule_84_A1_P172 LoadBasedOffsetMemory_Ldrsh_Rule_84_A1_P172_instance_;
   const NamedLoadBasedOffsetMemoryDouble_Ldrd_Rule_68_A1_P140 LoadBasedOffsetMemoryDouble_Ldrd_Rule_68_A1_P140_instance_;
   const NamedLoadMultiple_Ldm_Ldmia_Ldmfd_Rule_53_A1_P110 LoadMultiple_Ldm_Ldmia_Ldmfd_Rule_53_A1_P110_instance_;
   const NamedLoadMultiple_Ldmda_Ldmfa_Rule_54_A1_P112 LoadMultiple_Ldmda_Ldmfa_Rule_54_A1_P112_instance_;
   const NamedLoadMultiple_Ldmdb_Ldmea_Rule_55_A1_P114 LoadMultiple_Ldmdb_Ldmea_Rule_55_A1_P114_instance_;
   const NamedLoadMultiple_Ldmib_Ldmed_Rule_56_A1_P116 LoadMultiple_Ldmib_Ldmed_Rule_56_A1_P116_instance_;
   const NamedLoadMultiple_Pop_Rule_A1 LoadMultiple_Pop_Rule_A1_instance_;
-  const NamedMaskAddress_Bic_Rule_19_A1_P50 MaskAddress_Bic_Rule_19_A1_P50_instance_;
+  const NamedMaskAddress_BIC_immediate_A1 MaskAddress_BIC_immediate_A1_instance_;
   const NamedStoreBasedImmedMemory_Str_Rule_194_A1_P384 StoreBasedImmedMemory_Str_Rule_194_A1_P384_instance_;
   const NamedStoreBasedImmedMemory_Strb_Rule_197_A1_P390 StoreBasedImmedMemory_Strb_Rule_197_A1_P390_instance_;
   const NamedStoreBasedImmedMemory_Strh_Rule_207_A1_P410 StoreBasedImmedMemory_Strh_Rule_207_A1_P410_instance_;
   const NamedStoreBasedImmedMemoryDouble_Strd_Rule_200_A1_P396 StoreBasedImmedMemoryDouble_Strd_Rule_200_A1_P396_instance_;
   const NamedStoreBasedMemoryDoubleRtBits0To3_Strexd_Rule_204_A1_P404 StoreBasedMemoryDoubleRtBits0To3_Strexd_Rule_204_A1_P404_instance_;
   const NamedStoreBasedMemoryRtBits0To3_Strex_Rule_202_A1_P400 StoreBasedMemoryRtBits0To3_Strex_Rule_202_A1_P400_instance_;
   const NamedStoreBasedMemoryRtBits0To3_Strexb_Rule_203_A1_P402 StoreBasedMemoryRtBits0To3_Strexb_Rule_203_A1_P402_instance_;
   const NamedStoreBasedMemoryRtBits0To3_Strexh_Rule_205_A1_P406 StoreBasedMemoryRtBits0To3_Strexh_Rule_205_A1_P406_instance_;
   const NamedStoreBasedOffsetMemory_Str_Rule_195_A1_P386 StoreBasedOffsetMemory_Str_Rule_195_A1_P386_instance_;
   const NamedStoreBasedOffsetMemory_Strb_Rule_198_A1_P392 StoreBasedOffsetMemory_Strb_Rule_198_A1_P392_instance_;
   const NamedStoreBasedOffsetMemory_Strh_Rule_208_A1_P412 StoreBasedOffsetMemory_Strh_Rule_208_A1_P412_instance_;
   const NamedStoreBasedOffsetMemoryDouble_Strd_Rule_201_A1_P398 StoreBasedOffsetMemoryDouble_Strd_Rule_201_A1_P398_instance_;
-  const NamedTestIfAddressMasked_Tst_Rule_230_A1_P454 TestIfAddressMasked_Tst_Rule_230_A1_P454_instance_;
+  const NamedTestIfAddressMasked_TST_immediate_A1 TestIfAddressMasked_TST_immediate_A1_instance_;
   const NamedUndefined_Undefined_A5_2_5_0101 Undefined_Undefined_A5_2_5_0101_instance_;
   const NamedUndefined_Undefined_A5_2_5_0111 Undefined_Undefined_A5_2_5_0111_instance_;
   const NamedUndefined_Undefined_A5_6 Undefined_Undefined_A5_6_instance_;
   const NamedUnpredictable_Unpredictable Unpredictable_Unpredictable_instance_;
   const NamedVfpOp_Vabs_Rule_269_A2_P532 VfpOp_Vabs_Rule_269_A2_P532_instance_;
   const NamedVfpOp_Vadd_Rule_271_A2_P536 VfpOp_Vadd_Rule_271_A2_P536_instance_;
   const NamedVfpOp_Vcmp_Vcmpe_Rule_A1 VfpOp_Vcmp_Vcmpe_Rule_A1_instance_;
   const NamedVfpOp_Vcmp_Vcmpe_Rule_A2 VfpOp_Vcmp_Vcmpe_Rule_A2_instance_;
   const NamedVfpOp_Vcvt_Rule_297_A1_P582 VfpOp_Vcvt_Rule_297_A1_P582_instance_;
   const NamedVfpOp_Vcvt_Rule_298_A1_P584 VfpOp_Vcvt_Rule_298_A1_P584_instance_;
@@ skipping 76 matching lines @@
       const nacl_arm_dec::Instruction inst) const;
   inline const NamedClassDecoder& decode_unconditional_instructions(
       const nacl_arm_dec::Instruction inst) const;
   // Defines default action if parse tables don't define what action
   // to take.
   const NotImplementedNamed not_implemented_;
 };
 
 } // namespace nacl_arm_test
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_NAMED_DECODER_H_