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| 1 /* | 1 /* |
| 2 * Copyright 2012 The Native Client Authors. All rights reserved. | 2 * Copyright 2012 The Native Client Authors. All rights reserved. |
| 3 * Use of this source code is governed by a BSD-style license that can | 3 * Use of this source code is governed by a BSD-style license that can |
| 4 * be found in the LICENSE file. | 4 * be found in the LICENSE file. |
| 5 */ | 5 */ |
| 6 | 6 |
| 7 // DO NOT EDIT: GENERATED CODE | 7 // DO NOT EDIT: GENERATED CODE |
| 8 | 8 |
| 9 #ifndef NACL_TRUSTED_BUT_NOT_TCB | 9 #ifndef NACL_TRUSTED_BUT_NOT_TCB |
| 10 #error This file is not meant for use in the TCB | 10 #error This file is not meant for use in the TCB |
| (...skipping 276 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 287 } | 287 } |
| 288 | 288 |
| 289 | 289 |
| 290 /* | 290 /* |
| 291 * Implementation of table data_processing_immediate. | 291 * Implementation of table data_processing_immediate. |
| 292 * Specified by: ('See Section A5.2.3',) | 292 * Specified by: ('See Section A5.2.3',) |
| 293 */ | 293 */ |
| 294 const NamedClassDecoder& NamedArm32DecoderState::decode_data_processing_immediat
e( | 294 const NamedClassDecoder& NamedArm32DecoderState::decode_data_processing_immediat
e( |
| 295 const nacl_arm_dec::Instruction inst) const { | 295 const nacl_arm_dec::Instruction inst) const { |
| 296 UNREFERENCED_PARAMETER(inst); | 296 UNREFERENCED_PARAMETER(inst); |
| 297 if ((inst.Bits() & 0x01F00000) == 0x00400000 /* op(24:20)=00100 */ && | |
| 298 (inst.Bits() & 0x000F0000) == 0x000F0000 /* Rn(19:16)=1111 */) | |
| 299 return Unary1RegisterImmediateOp_Adr_Rule_10_A2_P32_instance_; | |
| 300 | |
| 301 if ((inst.Bits() & 0x01F00000) == 0x00500000 /* op(24:20)=00101 */ && | |
| 302 (inst.Bits() & 0x000F0000) == 0x000F0000 /* Rn(19:16)=1111 */ && | |
| 303 (inst.Bits() & 0x0000F000) == 0x0000F000 /* $pattern(31:0)=xxxxxxxxxxxxxxx
x1111xxxxxxxxxxxx */) | |
| 304 return ForbiddenCondDecoder_Subs_Pc_Lr_and_related_instructions_Rule_A1a_ins
tance_; | |
| 305 | |
| 306 if ((inst.Bits() & 0x01F00000) == 0x00800000 /* op(24:20)=01000 */ && | |
| 307 (inst.Bits() & 0x000F0000) == 0x000F0000 /* Rn(19:16)=1111 */) | |
| 308 return Unary1RegisterImmediateOp_Adr_Rule_10_A1_P32_instance_; | |
| 309 | |
| 310 if ((inst.Bits() & 0x01F00000) == 0x00900000 /* op(24:20)=01001 */ && | |
| 311 (inst.Bits() & 0x000F0000) == 0x000F0000 /* Rn(19:16)=1111 */ && | |
| 312 (inst.Bits() & 0x0000F000) == 0x0000F000 /* $pattern(31:0)=xxxxxxxxxxxxxxx
x1111xxxxxxxxxxxx */) | |
| 313 return ForbiddenCondDecoder_Subs_Pc_Lr_and_related_instructions_Rule_A1b_ins
tance_; | |
| 314 | |
| 315 if ((inst.Bits() & 0x01F00000) == 0x01100000 /* op(24:20)=10001 */ && | 297 if ((inst.Bits() & 0x01F00000) == 0x01100000 /* op(24:20)=10001 */ && |
| 316 (inst.Bits() & 0x0000F000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxxxxx
x0000xxxxxxxxxxxx */) | 298 (inst.Bits() & 0x0000F000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxxxxx
x0000xxxxxxxxxxxx */) |
| 317 return MaskedBinaryRegisterImmediateTest_Tst_Rule_230_A1_P454_instance_; | 299 return MaskedBinaryRegisterImmediateTest_TST_immediate_A1_instance_; |
| 318 | 300 |
| 319 if ((inst.Bits() & 0x01F00000) == 0x01300000 /* op(24:20)=10011 */ && | 301 if ((inst.Bits() & 0x01F00000) == 0x01300000 /* op(24:20)=10011 */ && |
| 320 (inst.Bits() & 0x0000F000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxxxxx
x0000xxxxxxxxxxxx */) | 302 (inst.Bits() & 0x0000F000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxxxxx
x0000xxxxxxxxxxxx */) |
| 321 return BinaryRegisterImmediateTest_Teq_Rule_227_A1_P448_instance_; | 303 return BinaryRegisterImmediateTest_TEQ_immediate_A1_instance_; |
| 322 | 304 |
| 323 if ((inst.Bits() & 0x01F00000) == 0x01500000 /* op(24:20)=10101 */ && | 305 if ((inst.Bits() & 0x01F00000) == 0x01500000 /* op(24:20)=10101 */ && |
| 324 (inst.Bits() & 0x0000F000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxxxxx
x0000xxxxxxxxxxxx */) | 306 (inst.Bits() & 0x0000F000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxxxxx
x0000xxxxxxxxxxxx */) |
| 325 return BinaryRegisterImmediateTest_Cmp_Rule_35_A1_P80_instance_; | 307 return BinaryRegisterImmediateTest_CMP_immediate_A1_instance_; |
| 326 | 308 |
| 327 if ((inst.Bits() & 0x01F00000) == 0x01700000 /* op(24:20)=10111 */ && | 309 if ((inst.Bits() & 0x01F00000) == 0x01700000 /* op(24:20)=10111 */ && |
| 328 (inst.Bits() & 0x0000F000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxxxxx
x0000xxxxxxxxxxxx */) | 310 (inst.Bits() & 0x0000F000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxxxxx
x0000xxxxxxxxxxxx */) |
| 329 return BinaryRegisterImmediateTest_Cmn_Rule_32_A1_P74_instance_; | 311 return BinaryRegisterImmediateTest_CMN_immediate_A1_instance_; |
| 330 | 312 |
| 331 if ((inst.Bits() & 0x01E00000) == 0x00000000 /* op(24:20)=0000x */) | 313 if ((inst.Bits() & 0x01E00000) == 0x00000000 /* op(24:20)=0000x */) |
| 332 return Binary2RegisterImmediateOp_And_Rule_11_A1_P34_instance_; | 314 return Binary2RegisterImmediateOp_AND_immediate_A1_instance_; |
| 333 | 315 |
| 334 if ((inst.Bits() & 0x01E00000) == 0x00200000 /* op(24:20)=0001x */) | 316 if ((inst.Bits() & 0x01E00000) == 0x00200000 /* op(24:20)=0001x */) |
| 335 return Binary2RegisterImmediateOp_Eor_Rule_44_A1_P94_instance_; | 317 return Binary2RegisterImmediateOp_EOR_immediate_A1_instance_; |
| 336 | 318 |
| 337 if ((inst.Bits() & 0x01E00000) == 0x00400000 /* op(24:20)=0010x */ && | 319 if ((inst.Bits() & 0x01E00000) == 0x00400000 /* op(24:20)=0010x */ && |
| 338 (inst.Bits() & 0x000F0000) != 0x000F0000 /* Rn(19:16)=~1111 */) | 320 (inst.Bits() & 0x000F0000) != 0x000F0000 /* Rn(19:16)=~1111 */) |
| 339 return Binary2RegisterImmediateOp_Sub_Rule_212_A1_P420_instance_; | 321 return Binary2RegisterImmediateOp_SUB_immediate_A1_instance_; |
| 322 |
| 323 if ((inst.Bits() & 0x01E00000) == 0x00400000 /* op(24:20)=0010x */ && |
| 324 (inst.Bits() & 0x000F0000) == 0x000F0000 /* Rn(19:16)=1111 */) |
| 325 return Unary1RegisterImmediateOp_ADR_A2_instance_; |
| 340 | 326 |
| 341 if ((inst.Bits() & 0x01E00000) == 0x00600000 /* op(24:20)=0011x */) | 327 if ((inst.Bits() & 0x01E00000) == 0x00600000 /* op(24:20)=0011x */) |
| 342 return Binary2RegisterImmediateOp_Rsb_Rule_142_A1_P284_instance_; | 328 return Binary2RegisterImmediateOp_RSB_immediate_A1_instance_; |
| 343 | 329 |
| 344 if ((inst.Bits() & 0x01E00000) == 0x00800000 /* op(24:20)=0100x */ && | 330 if ((inst.Bits() & 0x01E00000) == 0x00800000 /* op(24:20)=0100x */ && |
| 345 (inst.Bits() & 0x000F0000) != 0x000F0000 /* Rn(19:16)=~1111 */) | 331 (inst.Bits() & 0x000F0000) != 0x000F0000 /* Rn(19:16)=~1111 */) |
| 346 return Binary2RegisterImmediateOp_Add_Rule_5_A1_P22_instance_; | 332 return Binary2RegisterImmediateOp_ADD_immediate_A1_instance_; |
| 333 |
| 334 if ((inst.Bits() & 0x01E00000) == 0x00800000 /* op(24:20)=0100x */ && |
| 335 (inst.Bits() & 0x000F0000) == 0x000F0000 /* Rn(19:16)=1111 */) |
| 336 return Unary1RegisterImmediateOp_ADR_A1_instance_; |
| 347 | 337 |
| 348 if ((inst.Bits() & 0x01E00000) == 0x00A00000 /* op(24:20)=0101x */) | 338 if ((inst.Bits() & 0x01E00000) == 0x00A00000 /* op(24:20)=0101x */) |
| 349 return Binary2RegisterImmediateOp_Adc_Rule_6_A1_P14_instance_; | 339 return Binary2RegisterImmediateOp_ADC_immediate_A1_instance_; |
| 350 | 340 |
| 351 if ((inst.Bits() & 0x01E00000) == 0x00C00000 /* op(24:20)=0110x */) | 341 if ((inst.Bits() & 0x01E00000) == 0x00C00000 /* op(24:20)=0110x */) |
| 352 return Binary2RegisterImmediateOp_Sbc_Rule_151_A1_P302_instance_; | 342 return Binary2RegisterImmediateOp_SBC_immediate_A1_instance_; |
| 353 | 343 |
| 354 if ((inst.Bits() & 0x01E00000) == 0x00E00000 /* op(24:20)=0111x */) | 344 if ((inst.Bits() & 0x01E00000) == 0x00E00000 /* op(24:20)=0111x */) |
| 355 return Binary2RegisterImmediateOp_Rsc_Rule_145_A1_P290_instance_; | 345 return Binary2RegisterImmediateOp_RSC_immediate_A1_instance_; |
| 356 | 346 |
| 357 if ((inst.Bits() & 0x01E00000) == 0x01800000 /* op(24:20)=1100x */) | 347 if ((inst.Bits() & 0x01E00000) == 0x01800000 /* op(24:20)=1100x */) |
| 358 return Binary2RegisterImmediateOp_Orr_Rule_113_A1_P228_instance_; | 348 return Binary2RegisterImmediateOp_ORR_immediate_A1_instance_; |
| 359 | 349 |
| 360 if ((inst.Bits() & 0x01E00000) == 0x01A00000 /* op(24:20)=1101x */ && | 350 if ((inst.Bits() & 0x01E00000) == 0x01A00000 /* op(24:20)=1101x */ && |
| 361 (inst.Bits() & 0x000F0000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxx000
0xxxxxxxxxxxxxxxx */) | 351 (inst.Bits() & 0x000F0000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxx000
0xxxxxxxxxxxxxxxx */) |
| 362 return Unary1RegisterImmediateOp_Mov_Rule_96_A1_P194_instance_; | 352 return Unary1RegisterImmediateOp_MOV_immediate_A1_instance_; |
| 363 | 353 |
| 364 if ((inst.Bits() & 0x01E00000) == 0x01C00000 /* op(24:20)=1110x */) | 354 if ((inst.Bits() & 0x01E00000) == 0x01C00000 /* op(24:20)=1110x */) |
| 365 return MaskedBinary2RegisterImmediateOp_Bic_Rule_19_A1_P50_instance_; | 355 return MaskedBinary2RegisterImmediateOp_BIC_immediate_A1_instance_; |
| 366 | 356 |
| 367 if ((inst.Bits() & 0x01E00000) == 0x01E00000 /* op(24:20)=1111x */ && | 357 if ((inst.Bits() & 0x01E00000) == 0x01E00000 /* op(24:20)=1111x */ && |
| 368 (inst.Bits() & 0x000F0000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxx000
0xxxxxxxxxxxxxxxx */) | 358 (inst.Bits() & 0x000F0000) == 0x00000000 /* $pattern(31:0)=xxxxxxxxxxxx000
0xxxxxxxxxxxxxxxx */) |
| 369 return Unary1RegisterImmediateOp_Mvn_Rule_106_A1_P214_instance_; | 359 return Unary1RegisterImmediateOp_MVN_immediate_A1_instance_; |
| 370 | 360 |
| 371 // Catch any attempt to fall through... | 361 // Catch any attempt to fall through... |
| 372 return not_implemented_; | 362 return not_implemented_; |
| 373 } | 363 } |
| 374 | 364 |
| 375 | 365 |
| 376 /* | 366 /* |
| 377 * Implementation of table data_processing_register. | 367 * Implementation of table data_processing_register. |
| 378 * Specified by: ('See Section A5.2.1',) | 368 * Specified by: ('See Section A5.2.1',) |
| 379 */ | 369 */ |
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| 2001 decode_named(const nacl_arm_dec::Instruction inst) const { | 1991 decode_named(const nacl_arm_dec::Instruction inst) const { |
| 2002 return decode_ARMv7(inst); | 1992 return decode_ARMv7(inst); |
| 2003 } | 1993 } |
| 2004 | 1994 |
| 2005 const nacl_arm_dec::ClassDecoder& NamedArm32DecoderState:: | 1995 const nacl_arm_dec::ClassDecoder& NamedArm32DecoderState:: |
| 2006 decode(const nacl_arm_dec::Instruction inst) const { | 1996 decode(const nacl_arm_dec::Instruction inst) const { |
| 2007 return decode_named(inst).named_decoder(); | 1997 return decode_named(inst).named_decoder(); |
| 2008 } | 1998 } |
| 2009 | 1999 |
| 2010 } // namespace nacl_arm_test | 2000 } // namespace nacl_arm_test |
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