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Side by Side Diff: runtime/vm/simulator_arm.cc

Issue 1077823002: Adds a simarmv5te build and test target. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 5 years, 8 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include <setjmp.h> // NOLINT 5 #include <setjmp.h> // NOLINT
6 #include <stdlib.h> 6 #include <stdlib.h>
7 7
8 #include "vm/globals.h" 8 #include "vm/globals.h"
9 #if defined(TARGET_ARCH_ARM) 9 #if defined(TARGET_ARCH_ARM)
10 10
(...skipping 1710 matching lines...) Expand 10 before | Expand all | Expand 10 after
1721 int32_t rm_val = get_register(rm); 1721 int32_t rm_val = get_register(rm);
1722 int32_t rs_val = get_register(rs); 1722 int32_t rs_val = get_register(rs);
1723 int32_t rd_val = 0; 1723 int32_t rd_val = 0;
1724 switch (instr->Bits(21, 3)) { 1724 switch (instr->Bits(21, 3)) {
1725 case 1: 1725 case 1:
1726 // Registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 1726 // Registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
1727 // Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); 1727 // Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
1728 case 3: { 1728 case 3: {
1729 // Registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 1729 // Registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
1730 // Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd"); 1730 // Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
1731 if (TargetCPUFeatures::arm_version() != ARMv7) {
1732 UnimplementedInstruction(instr);
1733 break;
1734 }
1735 rd_val = get_register(rd); 1731 rd_val = get_register(rd);
1736 // fall through 1732 // fall through
1737 } 1733 }
1738 case 0: { 1734 case 0: {
1739 // Registers rd, rn, rm are encoded as rn, rm, rs. 1735 // Registers rd, rn, rm are encoded as rn, rm, rs.
1740 // Format(instr, "mul'cond's 'rn, 'rm, 'rs"); 1736 // Format(instr, "mul'cond's 'rn, 'rm, 'rs");
1741 int32_t alu_out = rm_val * rs_val; 1737 int32_t alu_out = rm_val * rs_val;
1742 if (instr->Bits(21, 3) == 3) { // mls 1738 if (instr->Bits(21, 3) == 3) { // mls
1739 if (TargetCPUFeatures::arm_version() != ARMv7) {
1740 UnimplementedInstruction(instr);
1741 break;
1742 }
1743 alu_out = -alu_out; 1743 alu_out = -alu_out;
1744 } 1744 }
1745 alu_out += rd_val; 1745 alu_out += rd_val;
1746 set_register(rn, alu_out); 1746 set_register(rn, alu_out);
1747 if (instr->HasS()) { 1747 if (instr->HasS()) {
1748 SetNZFlags(alu_out); 1748 SetNZFlags(alu_out);
1749 } 1749 }
1750 break; 1750 break;
1751 } 1751 }
1752 case 4: 1752 case 4:
(...skipping 2120 matching lines...) Expand 10 before | Expand all | Expand 10 after
3873 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception)); 3873 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception));
3874 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace)); 3874 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace));
3875 buf->Longjmp(); 3875 buf->Longjmp();
3876 } 3876 }
3877 3877
3878 } // namespace dart 3878 } // namespace dart
3879 3879
3880 #endif // !defined(HOST_ARCH_ARM) 3880 #endif // !defined(HOST_ARCH_ARM)
3881 3881
3882 #endif // defined TARGET_ARCH_ARM 3882 #endif // defined TARGET_ARCH_ARM
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