[x86] Support immediate indices for StoreWriteBarrier.

[x86] Support immediate indices for StoreWriteBarrier.

Ideally we would not need the StoreWriteBarrier instructions at all,
but represent the RecordWrite functionality as machine subgraph, but
that'll take some time to get there. In the mean time we can have a
shorter instruction sequence on Intel platforms by recognizing immediate
indices here.

R=svenpanne@chromium.org

Committed: https://crrev.com/4eff883bcecaf24dfdcc6441e4558a9f5e69bd55
Cr-Commit-Position: refs/heads/master@{#27731}

[Benedikt Meurer, 2015-04-10 05:51:58]

Hey Sven,

This is more or less obvious. Don't be confused with the
RecordWriteForContextSlot naming, it just means that the index is not tagged
(comment in MacroAssembler makes that clear, still a bad name). Please take a
look.

Thanks,
Benedikt

[Sven Panne, 2015-04-10 06:01:28]

The CQ bit was checked by svenpanne@chromium.org

[Sven Panne, 2015-04-10 06:01:28]

lgtm

[commit-bot: I haz the power, 2015-04-10 06:01:39]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1075103002/1

[commit-bot: I haz the power, 2015-04-10 06:16:31]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2015-04-10 06:16:47]

Patchset 1 (id:??) landed as
https://crrev.com/4eff883bcecaf24dfdcc6441e4558a9f5e69bd55
Cr-Commit-Position: refs/heads/master@{#27731}